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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2005 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs42528 114 db, 192 khz 8-ch codec with s/pdif receiver features z eight 24-bit d/a, two 24-bit a/d converters z 114 db dac / 114 db adc dynamic range z -100 db thd+n z system sampling rates up to 192 khz z s/pdif receiver compatible with eiaj cp1201 and iec-60958 z recovered s/pdif clock or system clock selection z 8:2 s/pdif input mux z adc high-pass filter for dc offset calibration z expandable adc channels and one-line mode support z digital output volume control with soft ramp z digital +/-15db input gain adjust for adc z differential analog architecture z supports logic levels between 5 v and 1.8 v. general description the cs42528 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrat- ed s/pdif receiver, in a 64-pin lqfp package. the cs42528 integrated s/pdif receiver supports up to eight inputs, clock recovery circuitry and format auto-detection. the internal stereo adc is capable of independent channel gain control for single-ended or differ ential analog inputs. all eight channels of dac provide digital volume control and differential analog outputs. the general purpose outputs may be driven high or low, or mapped to a variety of dac mute controls or adc overflow indicators. the cs42528 is ideal for audio systems requiring wide dynam- ic range, negligible distortion and low noise, such as a/v receivers, dvd receivers, digital speaker and automotive audio systems. ordering in formation cs42528-cqz -10 to 70 c 64-pin lqfp lead free CS42528-DQZ -40 to 85 c 64-pin lqfp lead free cdb42528 evaluation board rst rxp0 rxp1/gpo1 ad0/cs scl/cclk sda/cdout ad1/cdin vlc aouta1+ aouta1- aoutb1+ aouta3+ aouta3- aouta2- aoutb2- aouta2+ aoutb2+ aoutb1- aoutb3+ aoutb3- aouta4+ aouta4- aoutb4+ aoutb4- ainl+ ainl- ainr+ ainr- filt+ refgnd vq ref adc#1 adc#2 digital filter digital filter gain & clip gain & clip cx_sdout adcin1 adcin2 cx_sclk cx_lrck cx_sdin4 cx_sdin3 cx_sdin2 cx_sdin1 vls sai_lrck sai_sclk sai_sdout dgnd vd omck rmck lpflt txp int rx clock/data recovery s/pdif decoder dem serial audio interface port c&u bit data buffer control port dac#1 dac#2 dac#3 dac#4 dac#5 dac#6 dac#7 dac#8 d i g i t a l f i l t e r v o l u m e c o n t r o l dgnd rxp2/gpo2 rxp3/gpo3 rxp4/gpo4 rxp5/gpo5 rxp6/gpo6 rxp7/gpo7 vd mutec gpo mute a n a l o g f i l t e r varx agnd adc serial data agnd va internal mclk codec serial port mult/div format detector jan ?05 ds586pp5
cs42528 2 ds586pp5 table of contents 1. characteristics and specifications ........................................................................ 7 specified operating conditions ................................................................................................ 7 absolute maximum ratings ................................. ..................................................................... 7 analog input characteristics ................................................................................................... .. 8 a/d digital filter characteristics ............................................................................................. .. 9 analog output characteristics .......................... ...................................................................... 10 d/a digital filter characteristics ............................................................................................. 11 switching characteristics...................................................................................................... .. 12 switching characteristics - control port - i 2 c format............................................................. 13 switching characteristics - control port - spi tm format........................................................ 14 dc electrical characteristics .................................................................................................. 15 digital interface characteristics .............................................................................................. 16 2. pin descriptions .......................................................................................................... .... 17 3. typical connection diagram .................................................................................. 20 4. applications .............................................................................................................. ........ 21 4.1 overview .................................................................................................................. ........ 21 4.2 analog inputs ............................................................................................................. ...... 21 4.2.1 line level inputs ................................................................................................. 21 4.2.2 high pass filter and dc offset calibration ......................................................... 22 4.3 analog outputs ............................................................................................................ .... 22 4.3.1 line level outputs and filtering ......................................................................... 22 4.3.2 interpolation filter ............................................................................................... 22 4.3.3 digital volume and mute control ........................................................................ 23 4.3.4 atapi specification ............................................................................................ 23 4.4 s/pdif receiver ........................................................................................................... ... 24 4.4.1 8:2 s/pdif input multiplexer ............................................................................... 24 4.4.2 error reporting and hold function ..................................................................... 24 4.4.3 channel status data h andling ............................................................................ 24 4.4.4 user data handling ............................................................................................. 24 4.4.5 non-audio auto-detection .................. ................................................................ 24 4.5 clock generation .......................................................................................................... ... 25 4.5.1 pll and jitter attenuation ................................................................................... 25 4.5.2 omck system clock mo de ................................................................................ 26 4.5.3 master mode ....................................................................................................... 26 4.5.4 slave mode ......................................................................................................... 26 4.6 digital interfaces ........................................................................................................ ...... 27 4.6.1 serial audio interface signals ............................................................................. 27 4.6.2 serial audio interface formats ......... ................................................................... 29 4.6.3 adcin1/adcin2 serial da ta format .................................................................. 32 4.6.4 one line mode(olm) configurations ................................................................. 33 4.6.4a olm config #1 ..................................................................................... 33 4.6.4b olm config #2 ..................................................................................... 34 4.6.4c olm config #3 ..................................................................................... 35 4.6.4d olm config #4 ..................................................................................... 36 4.6.4e olm config #5 ..................................................................................... 37 4.7 control port descrip tion and timing ................................................................................ 38 4.7.1 spi mode ............................................................................................................ 38 4.7.2 i 2 c mode ............................................................................................................. 39 4.8 interrupts ................................................................................................................ .......... 40 4.9 reset and power-up ....................................................................................................... 40 4.10 power supply, grou nding, and pcb layout ................................................................... 40
ds586pp5 3 cs42528 5. register quick reference .......................................................................................... 42 6. register description .................................................................................................... 47 6.1 memory address pointer (map) ....................................................................................... 47 6.2 chip i.d. and revision register (address 01h) (read only) ............................................ 47 6.3 power control (address 02h)............................................................................................ 48 6.4 functional mode (address 03h)........................................................................................ 49 6.5 interface formats (address 04h) ...................................................................................... 50 6.6 misc control (address 05h) .............................................................................................. 52 6.7 clock control (address 06h) ............................................................................................. 53 6.8 omck/pll_clk ratio (address 07h) (read only) ......................................................... 55 6.9 rvcr status (address 08h) (read only)......................................................................... 55 6.10 burst preamble pc and pd bytes (addre sses 09h - 0ch)(read only).......................... 56 6.11 volume transition control (address 0dh) ...................................................................... 57 6.12 channel mute (address 0eh).................... ...................................................................... 59 6.13 volume control (add resses 0fh, 10h, 11h, 12h , 13h, 14h, 15h, 16h) ........................ 59 6.14 channel invert (address 17h) ......................................................................................... 59 6.15 mixing control pair 1 (channels a1 & b1)(address 18h) mixing control pair 2 (channels a2 & b2)(address 19h) mixing control pair 3 (channels a3 & b3)(address 1ah) mixing control pair 4 (channels a4 & b4)( address 1bh) ............................................ 60 6.16 adc left channel gain (address 1ch) .......................................................................... 62 6.17 adc right channel gain (address 1dh) ........................................................................ 62 6.18 receiver mode control (address 1eh) ........................................................................... 62 6.19 receiver mode control 2 (address 1fh) .. ...................................................................... 63 6.20 interrupt status (address 20h) (read only) ................................................................... 64 6.21 interrupt mask (address 21h) ......................................................................................... 65 6.22 interrupt mode msb (address 22h) interrupt mode lsb (a ddress 23h)................................................................................ 65 6.23 channel status data buffer control (address 24h) ........................................................ 66 6.24 receiver channel status (address 25h) (read only) .................................................... 67 6.25 receiver errors (address 26h) (read on ly) ................................................................... 68 6.26 receiver errors mask (address 27h) .............................................................................. 69 6.27 mutec pin control (address 28h) ................ ................................................................... 69 6.28 rxp/general purpose pin control (address es 29h to 2fh) ........................................... 70 6.29 q-channel subcode bytes 0 to 9 (addresses 30h to 39h) (read only)......................... 72 6.30 c-bit or u-bit data buffer (addresses 3a h to 51h) (read only) ..................................... 72 7. parameter definitions .................................................................................................. 73 8. references ................................................................................................................ ........ 74 9. package dimensions ................................................................................................... 75 thermal characteristics ........................................................................................... 75 10. appendix a: external filters ................................................................................... 76 10.1 adc input filter ......................................................................................................... .... 76 10.2 dac output filter ........................................................................................................ .. 76 11. appendix b: s/pdif receiver ....................................................................................... 77 11.1 error reporting and hold function ................................................................................ 77 11.2 channel status data handling ...................................................................................... 77 11.2.1 channel status data e buffer access .............................................................. 78 11.2.1a one byte mode .................................................................................. 78 11.2.1b two byte mode .................................................................................. 78 11.2.2 serial copy management system (s cms) ....................................................... 79 11.3 user (u) data e buffer access ...................................................................................... 79 11.3.1 non-audio auto-detection ................................................................................ 79 11.3.1a format detection ...................... ......................................................... 79
cs42528 4 ds586pp5 12. appendix c: pll filter .................................................................................................. 8 0 12.1 external filter component s ........................................................................................... 81 12.1.1 general ............................................................................................................. 81 12.1.2 jitter attenuation ..... .......................................................................................... 81 12.1.3 capacitor selection . .......................................................................................... 82 12.1.4 circuit board layout .......................................................................................... 82 13. appendix d: external aes3/spdif/iec60958 receiver components .............. 83 13.1 aes3 receiver external components ........................................................................... 83 14. appendix e: adc filter plots .................................................................................... 84 15. appendix f: dac filter plots .................................................................................... 86 list of figures figure 1. serial audio port master mode timing .......................................................................... 12 figure 2. serial audio port slave mode timing ............................................................................ 12 figure 3. control port timing - i 2 c format ................................................................................... 13 figure 4. control port timing - spi format...... ............................................................................. 14 figure 5. typical connection diagram .......................................................................................... 2 0 figure 6. full-scale analog input .................. ............................................................................ .... 21 figure 7. full-scale output .................................................................................................... ....... 22 figure 8. atapi block diagram (x = channel pair 1, 2, 3, 4)......................................................... 23 figure 9. cs42528 clock generation ........................................................................................... 25 figure 10. i 2 s serial audio formats.............................. ................................................................ 29 figure 11. left justified serial audio formats .............................................................................. 30 figure 12. right justified serial audio formats .. .......................................................................... 30 figure 13. one line mode #1 seri al audio format....................................................................... 31 figure 14. one line mode #2 seri al audio format....................................................................... 31 figure 15. adcin1/adcin2 serial audio format ......................................................................... 32 figure 16. olm configuration #1 ................................................................................................ .. 33 figure 17. olm configuration #2 ................................................................................................ .. 34 figure 18. olm configuration #3 ................................................................................................ .. 35 figure 19. olm configuration #4 ................................................................................................ .. 36 figure 20. olm configuration #5 ................................................................................................ .. 37 figure 21. control port timing in spi mode..... ............................................................................. 38 figure 22. control port timing, i 2 c write...................................................................................... 39 figure 23. control port timing, i 2 c read ..................................................................................... 39 figure 24. recommended analog input buffer ............................................................................. 76 figure 25. recommended analog output buffer .......................................................................... 76 figure 26. channel status data buffer structure.......................................................................... 78 figure 27. pll block diagram ... ................................................................................................ ... 80 figure 28. jitter attenuation characteristics of pll ...................................................................... 81 figure 29. recommended layout example ............ ...................................................................... 82 figure 30. consumer input circuit ................... ........................................................................... .. 83 figure 31. s/pdif mux input circuit .................. .......................................................................... 83 figure 32. ttl/cmos input circuit.............................................................................................. .83 figure 33. single speed mode st opband rejection ..................................................................... 84 figure 34. single speed mode transition band............................................................................ 84 figure 35. single speed mode transition band (detail) ............................................................... 84 figure 36. single speed mode passband ripple.... ...................................................................... 84 figure 37. double speed mode st opband rejection .................................................................... 84 figure 38. double speed mode transition band .......................................................................... 84 figure 39. double speed mode tr ansition band (detail).............................................................. 85 figure 40. double speed mode pa ssband ripple ........................................................................ 85 figure 41. quad speed mode stop band rejection....................................................................... 85
ds586pp5 5 cs42528 figure 42. quad speed mode transition band....... ...................................................................... 85 figure 43. quad speed mode transition band (d etail) ................................................................ 85 figure 44. quad speed mode passband ripple..... ...................................................................... 85 figure 45. single speed (fast) stopband rejection ...................................................................... 86 figure 46. single speed (fast) transition band ............................................................................ 86 figure 47. single speed (fast) transition band (detail) ................................................................ 86 figure 48. single speed (fast) passband ripple .......................................................................... 86 figure 49. single speed (slow) stopband rejection..................................................................... 86 figure 50. single speed (slow) transition band........................................................................... 86 figure 51. single speed (slow) transition band (detail)............................................................... 87 figure 52. single speed (slow) passband ripple......................................................................... 87 figure 53. double speed (fast) stopband rejection..................................................................... 87 figure 54. double speed (fast) transition band ........................................................................... 87 figure 55. double speed (fast) transition band (detail)............................................................... 87 figure 56. double speed (fast) passband ripple ......................................................................... 87 figure 57. double speed (slow) stopband rejection ................................................................... 88 figure 58. double speed (slow) transition band ......................................................................... 88 figure 59. double speed (slow) transition band (detail) ............. ................................................ 88 figure 60. double speed (slow) passband ripple ....................................................................... 88 figure 61. quad speed (fast) stopband rejection . ...................................................................... 88 figure 62. quad speed (fast) tr ansition band ............................................................................. 88 figure 63. quad speed (fast) tran sition band (detail) ................................................................. 89 figure 64. quad speed (fast) passband ripple ........................................................................... 89 figure 65. quad speed (slow) st opband rejection...................................................................... 89 figure 66. quad speed (slow) tr ansition band ............................................................................ 89 figure 67. quad speed (slow) transition band (det ail) ................................................................ 89 figure 68. quad speed (slow) pa ssband ripple .......................................................................... 89
cs42528 6 ds586pp5 list of tables table 1. common omck clock frequencies ............................................................................... 26 table 2. common pll output clock frequencies.. ...................................................................... 26 table 3. slave mode clock ratios ............................................................................................... .26 table 4. serial audio port channel allocations ............................................................................. 27 table 5. dac de-emphasis ....................................................................................................... ... 50 table 6. receiver de-emphasis.................................................................................................. .. 50 table 7. digital interface form ats ............................................................................................. .... 51 table 8. adc one-line mode ..................................................................................................... .. 51 table 9. dac one-line mode ..................................................................................................... .. 51 table 10. rmck divider settings........................ ........................................................................ .. 53 table 11. omck frequency settings...................... ...................................................................... 54 table 12. master clock source se lect .......................................................................................... 5 4 table 13. aes format dete ction............. ................ ................ ................ ............. ............. .......... .. 55 table 14. receiver clock frequen cy detection ............................................................................ 56 table 15. example digital volume settings ............ ...................................................................... 59 table 16. atapi decode......................................................................................................... ...... 61 table 17. example adc input gain settings .......... ...................................................................... 62 table 18. txp output selection....................... .......................................................................... ... 63 table 19. receiver input selection ............................................................................................. .. 64 table 20. auxiliary data width selection ...................................................................................... 6 7 table 21. pll external component values ............ ...................................................................... 81 table 22. revision history ................................................................................................... ....... 90
ds586pp5 7 cs42528 1. characteristics and specifications (all min/max characteristics and specifications are guarante ed over the specified operat ing conditions. typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and t a = 25 c.) specified operat ing conditions (agnd=dgnd=0, all voltages with respect to ground; omck=12.288 mhz; master mode) absolute maximum ratings (agnd = dgnd = 0 v; all voltag es with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. any pin except supplies. tran sient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 2. the maximum over/under voltage is limited by the input current. parameter symbol min typ max units dc power supply analog digital serial port interface control port interface va / varx vd vls vlc 4.75 3.13 1.8 1.8 5.0 3.3 5.0 5.0 5.25 5.25 5.25 5.25 v v v v ambient operating temperature (power applied) cs42528-cqz CS42528-DQZ t a -10 -40 - - +70 +85 c c parameters symbol min max units dc power supply analog digital serial port interface control port interface va / varx vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 v v v v input current (note 1) i in -10ma analog input voltage (note 2) v in agnd-0.7 va+0.7 v digital input voltage serial port interface (note 2) control port interface s/pdif interface v ind-s v ind-c v ind-sp -0.3 -0.3 -0.3 vls+ 0.4 vlc+ 0.4 varx+0.4 v v v ambient operating temperature(power applied) cs42528-cqz CS42528-DQZ t a t a -20 -50 +85 +95 c c storage temperature t stg -65 +150 c
cs42528 8 ds586pp5 analog input characteristics (t a = 25 c; va =varx= 5 v, vd = 3.3 v, logic "0" = dgnd =agnd = 0 v; logic "1" = vls = vlc = 5 v; measurement bandwidth is 10 hz to 20 khz unless otherwise specified. full scale input sine wave , 997 hz.; pdn_rcvr = 1; sw_ctrl[ 1:0] = ?01?; omck = 12.288 mhz; sin- gle speed mode cx_sclk = 3.072 mhz; double speed mode cx_sclk = 6.144 mhz; quad speed mode cx_sclk = 12.288 mhz.) notes: 3. referred to the typical full-scale voltage. 4. measured between ain+ and ain- parameter symbol cs42528-cqz min typ max CS42528-DQZ min typ max unit single speed mode (fs=48 khz) dynamic range a-weighted unweighted 108 105 114 111 - - 106 103 114 111 - - db db total harmonic distortion + noise (note 3) -1 db -20 db -60 db thd+n - - - -100 -91 -51 -94 - - - - - -100 -91 -51 -92 - - db db db double speed mode (fs=96 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - 106 103 - 114 111 108 - - - db db db total harmonic distortion + noise (note 3) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -100 -91 -51 -97 -94 - - - - - - - -100 -91 -51 -97 -92 - - - db db db db quad speed mode (fs=192 khz) dynamic range a-weighted unweighted 40 khz bandwidth unweighted 108 105 - 114 111 108 - - - 106 103 - 114 111 108 - - - db db db total harmonic distortion + noise (note 3) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -100 -91 -51 -97 -94 - - - - - - - -100 -91 -51 -97 -92 - - - db db db db dynamic performance for all modes interchannel isolation - 110 - - 110 - db interchannel phase deviation - 0.0001 - - 0.0001 - degree dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - +/-100 - - +/-100 - ppm/c offset error hpf_freeze disabled hpf_freeze enabled - - 0 100 - - - - 0 100 - - lsb lsb analog input full-scale differential input voltage 1.05 va 1.10 va 1.16 va 0.99 va 1.10 va 1.21 va vpp input impedance(differential) (note 4) 17 - - 17 - - k ? common mode rejection ratio cmrr - 82 - - 82 - db
ds586pp5 9 cs42528 a/d digital filter characteristics notes: 5. the filter frequency res ponse scales precisely with fs. 6. response shown is for fs equal to 48 khz. filter characteristics scale with fs. parameter symbol min typ max unit single speed mode (2 to 50 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.47 fs passband ripple - - 0.035 db stopband (note 5) 0.58 - - fs stopband attenuation -95 - - db total group delay (fs = output sample rate) t gd -12/fs- s group delay variation vs. frequency ? t gd --0.0 s double speed mode (50 to 100 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.45 fs passband ripple - - 0.035 db stopband (note 5) 0.68 - - fs stopband attenuation -92 - - db total group delay (fs = output sample rate) t gd -9/fs- s group delay variation vs. frequency ? t gd --0.0 s quad speed mode (100 to 192 khz sample rates) passband (-0.1 db) (note 5) 0 - 0.24 fs passband ripple - - 0.035 db stopband (note 5) 0.78 - - fs stopband attenuation -97 - - db total group delay (fs = output sample rate) t gd -5/fs- s group delay variation vs. frequency ? t gd --0.0 s high pass filter characteristics frequency response -3.0 db -0.13 db (note 6) -1 20 - - hz hz phase deviation @ 20 hz (note 6) - 10 - deg passband ripple - - 0 db filter setting time - 10 5 /fs - s
cs42528 10 ds586pp5 analog output characteristics (t a = 25 c; va =varx= 5 v, vd = 3.3 v, logic "0" = dgnd =agnd = 0 v; logic "1" = vls = vlc = 5v; measurement bandwidth 10 hz to 20 khz unless otherwise specified.; full scale output 99 7 hz sine wave, test load r l = 3 k ? , c l = 30 pf; pdn_rcvr = 1; sw_ctrl[1:0] = ?01?; omck = 12.288 mhz; single s peed mode, cx_sclk = 3.072 mhz; double speed mode, cx_sclk = 6.144 mhz; quad speed mode, cx_sclk = 12.288 mhz.) notes: 7. one-half lsb of triangular pdf dither is added to data. 8. performance limited by 16-bit quantization noise. parameter symbol cs42528-cqz min typ max CS42528-DQZ min typ max unit dynamic performance for all modes dynamic range(note 7) 24-bit a-weighted unweighted 16-bit a-weighted (note 8) unweighted 108 105 - - 114 111 97 94 - - - - 106 103 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db 16-bit 0 db (note 8) -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - - - - - - - - - - -100 -91 -51 -94 -74 -34 -92 - - - - - db db db db db db idle channel noise/signal-to- noise ratio (a-weighted) -114 - - 114 - db interchannel isolation (1 khz) - 90 - - 90 - db analog output characteristics for all modes unloaded full scale differential output voltage v fs .89va .94va .99va .84va .94va 1.04va vpp interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 300 - - 300 - ppm/c output impedance z out -150 - - 150 - ? ac-load resistance r l 3- -3 - -k ? load capacitance c l - - 30 - - 30 pf
ds586pp5 11 cs42528 d/a digital filter characteristics notes: 9. response is clock dependent and w ill scale with fs. note that the response plots (figures 45 to 68) have been normalized to fs and can be de-normalized by multiplying the x- axis scale by fs. 10. single and double speed mode measurement bandwidth is from stopband to 3 fs. quad speed mode measurement bandwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single speed mode. parameter fast roll-off slow roll-off unit min typ max min typ max combined digital and on-chip analog filter response - single speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.4535 0.4998 0 0 - - 0.4166 0.4998 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 -0.01 - +0.01 db stopband 0.5465 - - 0.5834 - - fs stopband attenuation (note 10) 90 - - 64 - - db group delay - 12/fs - - 6.5/fs - s passband group delay deviation 0 - 20 khz - - 0.41/fs - 0.14/fs s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filter response - double speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.4166 0.4998 0 0 - - 0.2083 0.4998 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband 0.5834 - - 0.7917 - - fs stopband attenuation (note 10) 80 - - 70 - - db group delay - 4.6/fs - - 3.9/fs - s passband group delay deviation 0 - 20 khz - - 0.03/fs - 0.01/fs s combined digital and on-chip analog filter response - quad speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.1046 0.4897 0 0 - - 0.1042 0.4813 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 -0.01 - 0.01 db stopband 0.6355 - - 0.8683 - - fs stopband attenuation (note 10) 90 - - 75 - - db group delay - 4.7/fs - - 4.2/fs - s passband group delay deviation 0 - 20 khz - - 0.01/fs - 0.01/fs s
cs42528 12 ds586pp5 switching characteristics (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va=varx = 5 v, vd =vlc= 3.3 v, vls = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vls, c l = 30 pf) notes: 12. after powering up the cs42528, rst should be held low after the powe r supplies and clocks are settled. 13. see table 1 on page 26 for suggested omck frequencies 14. limit the loading on rmck to 1 cmos load if operating above 24.576 mhz. 15. not valid when rmck_div in ?clock control (add ress 06h)? on page 53 is set to multiply by 2. parameters symbol min typ max units rst pin low pulse width (note 12) 1 - - ms pll clock recovery sample rate range 30 - 200 khz rmck output jitter (note 14) - 200 - ps rms rmck output duty cycle (note 15) 45 50 55 % omck frequency (note 13) 1.024 - 25.600 mhz omck duty cycle (note 13) 40 50 60 % cx_sclk, sai_sclk duty cycle 45 50 55 % cx_lrck, sai_lrck duty cycle 45 50 55 % master mode rmck to cx_sclk, sai_sclk active edge delay t smd 0-15ns rmck to cx_lrck, sai_lrck delay t lmd 0-15ns slave mode cx_sclk, sai_sclk falling edge to cx_sdout, sai_sdout output valid t dpd -50ns cx_lrck, sai_lrck edge to msb valid t lrpd -20ns cx_sdin setup time before cx_sclk rising edge t ds 10 - - ns cx_sdin hold time after cx_sclk rising edge t dh 30 - - ns cx_sclk, sai_sclk high time t sckh 20 - - ns cx_sclk, sai_sclk low time t sckl 20 - - ns cx_sclk, sai_sclk falling to cx_lrck, sai_lrck edge t lrck -25 - +25 ns cx_sclk sai_sclk (output) rmck t smd t lmd cx_lrck sai_lrck (output) sckh sckl t t msb msb-1 t dpd cx_sdout sai_sdout cx_sdinx dh t ds t lrpd t lrck t cx_sclk sai_sclk (input) cx_lrck sai_lrck (input) figure 1. serial audio port master mode timing figure 2. serial audio port slave mode timing
ds586pp5 13 cs42528 switching characteristics - control port - i 2 c format (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va=varx = 5 v, vd =vls = 3.3 v; vlc = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vlc, c l =30pf) notes: 16. data must be held for sufficient time to brid ge the transition time, t fc , of scl. 17. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 18. for single-speed mode, for double-speed mode, for quad-speed mode parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 17) t ack - (note 18) ns 15 256 fs -------------------- - 15 128 fs -------------------- - 15 64 fs ----------------- - t buf t hdst t lo w t hdd t high t sud stop s tart sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 3. control port timing - i 2 c format
cs42528 14 ds586pp5 switching characteristics - control port - spi tm format (for cqz, t a = -10 to +70 c; for dqz, t a = -40 to +85 c; va=varx = 5 v, vd =vls= 3.3 v; vlc = 1.8 v to 5.25 v; inputs: logic 0 = dgnd, logic 1 = vlc, c l =30pf) notes: 19. if fs is lower than 46.875 khz, the maximum ccl k frequency should be less than 128 fs. this is dictated by the timing requirements necessary to access the channel status and user bit buffer memory. access to the control register file can be carried out at the full 6 mhz rate. the minimum allowable input sample rate is 8 khz, so choosing cclk to be less than or equal to 1.024 mhz should be safe for all possible conditions. 20. data must be held for sufficient time to bridge the transition time of cclk. 21. for f sck <1 mhz. parameter symbol min typ max units cclk clock frequency (note 19) f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 20) t dh 15 - - ns cclk falling to cdout stable t pd - - 50 ns rise time of cdout t r1 - - 25 ns fall time of cdout t f1 - - 25 ns rise time of cclk and cdin (note 21) t r2 - - 100 ns fall time of cclk and cdin (note 21) t f2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 4. control port timing - spi format
ds586pp5 15 cs42528 dc electrical characteristics (t a = 25 c; agnd=dgnd=0, all voltages with respect to ground; omck=12.288 mhz; master mode) notes: 22. current consumption increases with increasing fs and increasing omck. max values are based on highest fs and highest omck. variance between speed modes is negligible. 23. i lc measured with no external loading on the sda pin. 24. power down mode is defined as rst pin = low with all clock and data lines held static. 25. valid with the recommended capacitor values on filt+ and vq as shown in figure 5. parameter symbol min typ max units power supply current normal op eration, va = varx = 5 v (note 22) vd = 5 v vd = 3.3 v interface current, vlc=5 v (note 23) vls=5 v power-down state (all supplies) (note 24) i a i d i d i lc i ls i pd - - - - - - 75 85 51 250 13 250 - - - - - - ma ma ma a ma a power consumption (note 22) va=varx=5 v, vd=vls=vlc=3.3 v normal operation power-down (note 24) va=varx=5 v, vd=vls=vlc=5 v normal operation power-down (note 24) - - - - 587 1.25 866 1.25 650 - 960 - mw mw mw mw power supply rejection ratio (note 25) (1 khz) (60 hz) psrr - - 60 40 - - db db vq nominal voltage vq output impedance vq maximum allowable dc current - - - 2.7 50 0.01 - - - v k ? ma filt+ nominal voltage filt+ output impedance filt+ maximum allowable dc current - - - 5.0 35 0.01 - - - v k ? ma
cs42528 16 ds586pp5 digital interface characteristics (for cqz, t a = +25 c; for dqz, t a = -40 to +85 c) notes: 26. serial port signals include: rmck, omck, sai_sclk, sai_lrck , sai_sdout, cx_sclk, c x _ l r c k , c x _ s d o u t , c x _ s d i n 1 - 4 a d c i n 1 / 2 control port signals include: scl/cclk, sda/cdout, ad0/cs , ad1/cdin, int, rst s/pdif-gpo interface signals include: rxp0, rxp/gpo[1:7] 27. when operating rmck above 24.576 mhz, limi t the loading on the signal to 1 cmos load. parameters (note 26) symbol min typ max units high-level input voltage serial port control port v ih 0.7xvls 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvls 0.2xvlc v v high-level output voltage at i o =2 ma (note 27)serial port control port mutec, gpox txp v oh vls-1.0 vlc-1.0 va-1.0 vd-1.0 - - - - - - - - v v v v low-level output voltage at i o =2 ma (note 27) serial port, control port, mutec, gpox,txp v ol --0.4v input sensitivity, rxp[7:0] v th -150200mvpp input leakage current i in --10 a input capacitance - 8 - pf mutec drive current - 3 - ma
ds586pp5 17 cs42528 2. pin descriptions pin name # pin description cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 1 64 63 62 codec serial audio data input ( input ) - input for two?s complement serial audio data. cx_sclk 2 codec serial clock (input/output) - serial clock for the codec serial audio interface. cx_lrck 3 codec left right clock ( input / output ) - determines which channel, left or right, is currently active on the codec serial audio data line. vd 4 51 digital power ( input ) - positive power supply for the digital section. dgnd 5 52 digital ground ( input ) - ground reference. should be connected to digital ground. vlc 6 control port power ( input ) - determines the required signal level for the control port. scl/cclk 7 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i 2 c mode as shown in the typical connection diagram. sda/cdout 8 serial control data ( input/output ) - sda is a data i/o line in i 2 c mode and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram. cdout is the output data line for the control port interface in spi mode. ad1/cdin 9 address bit 1 (i 2 c)/serial control data (spi) ( input ) - ad1 is a chip address pin in i 2 c mode; cdin is the input data line for the control port interface in spi mode. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cx_sdin1 sai_sclk sai_lrck vd dgnd vlc scl/cclk sda/cdout ad1/cdin ad0/cs int rst ainr- ainr+ ainl+ ainl- vq filt+ refgnd aoutb4- aoutb4+ aouta4+ aouta4- va agnd aoutb3- aoutb3+ aouta3+ aouta3- aoutb2- aoutb2+ aouta2+ aouta2- aoutb1- aoutb1+ aouta1+ aouta1- mutec agnd varx rxp7/gpo7 rxp6/gpo6 rxp5/gpo5 rxp4/gpo4 rxp3/gpo3 rxp2/gpo2 rxp1/gpo1 lpflt rxp0 txp vd dgnd vls sai_sdou t rmck cx_sdout adcin2 adcin1 omck cx_lrck cx_sclk cx_sdin4 cx_sdin3 cx_sdin2 cs42528
cs42528 18 ds586pp5 ad0/cs 10 address bit 0 (i 2 c)/control port chip select (spi) (input ) - ad0 is a chip address pin in i 2 c mode; cs is the chip select signal in spi mode. int 11 interrupt (output ) - the cs42528 will generate an interrupt condition as per the interrupt mask register. see ?interrupts? on page 40 for more details. rst 12 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. ainr- ainr+ 13 14 differential right ch annel analog input ( input ) - signals are presented differentially to the delta-sigma modulators via the ainr+/- pins. ainl+ ainl- 15 16 differential left channel analog input ( input ) - signals are presented differentially to the delta-sigma modulators via the ainl+/- pins. vq 17 quiescent voltage ( output ) - filter connection for internal quiescent reference voltage. filt+ 18 positive voltage reference ( output ) - positive refe rence voltage for the internal sampling circuits. refgnd 19 reference ground ( input ) - ground reference for the internal sampling circuits. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- aouta4 +,- aoutb4 +,- 36,37 35,34 32,33 31,30 28,29 27,26 22,23 21,20 differential analog output ( output ) - the full-scale differential analog output level is specified in the analog characteristics specification table. va varx 24 41 analog power ( input ) - positive power supply for the analog section. agnd 25 40 analog ground ( input ) - ground reference. should be connected to analog ground. mutec 38 mute control ( output ) - the mute control pin outputs high impedance following an initial power-on con- dition or whenever the pdn bit is set to a ?1?, forcing the codec into power-down mode. the signal will remain in a high impedance state as long as the par t is in power-down mode. the mute control pin goes to the selected ?active? state during reset, muting, or if the master clock to left/right clock frequency ratio is incorrect. this pin is intended to be used as a co ntrol for external mute circuits to prevent the clicks and pops that can occur in any single supply system. the use of external mute circuits are not manda- tory but may be desired fo r designs requiring the absolute mi nimum in extraneou s clicks and pops. lpflt 39 pll loop filter ( output ) - an rc network should be connected between this pin and ground. rxp7/gpo7 rxp6/gpo6 rxp5/gpo5 rxp4/gpo4 rxp3/gpo3 rxp2/gpo2 rxp1/gpo1 42 43 44 45 46 47 48 s/pdif receiver input/ general purpose output ( input/output ) - receiver inputs for s/pdif encoded data. the cs42528 has an internal 8:2 multiplexer to select the active receiver port, according to the receiver mode control 2 register. these pins can also be configured as general purpose output pins, adc overflow indicators or mute control outputs according to the rxp/general purpose pin control registers. rxp0 49 s/pdif receiver input ( input ) - dedicated receiver input for s/pdif encoded data. txp 50 s/pdif transmitter output ( output ) - s/pdif encoded data output, mapped directly from one of the receiver inputs as indicated by the receiver mode control 2 register. vls 53 serial port interface power ( input ) - determines the required signal level for the serial port interfaces. sai_sdout 54 serial audio interface serial data output ( output ) - output for two?s complement serial audio pcm data from the s/pdif incoming stream. this pin can also be configured to transmit the output of the inter- nal and external adcs. rmck 55 recovered master clock ( output ) - recovered master clock output from the external clock reference (omck, pin 59) or the pll which is locked to the incoming s/pdif stream or cx_lrck.
ds586pp5 19 cs42528 cx_sdout 56 codec serial data output ( output ) - output for two?s complement serial audio data from the internal and external adcs. adcin1 adcin2 58 57 external adc serial input ( input ) - the cs42528 provides for up to two external stereo analog to digital converter inputs to provide a maximum of six channels on one serial data output line when the cs42528 is placed in one line mode. omck 59 external reference clock ( input ) - external clock reference that must be within the ranges specified in the register ?omck frequency (omck freqx)? on page 54. sai_lrck 60 serial audio interface left/right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. sai_sclk 61 serial audio interf ace serial clock (input/output) - serial clock for the serial audio interface.
cs42528 20 ds586pp5 3. typical connection diagram vd aouta1+ 24 0.1 f + 10 f 100 f 0.1 f + + 17 18 vq filt+ 36 37 0.1 f 4.7 f va + 10 f 51 aouta1- aoutb1+ 35 34 aoutb1- aouta2+ 32 33 aouta2- aoutb2+ 31 30 aoutb2- aouta3+ 28 29 aouta3- aoutb3+ 27 26 aoutb3- aouta4+ 22 23 aouta4- aoutb4+ 21 20 aoutb4- mutec 38 25 dgnd dgnd 5 refgnd 19 41 4 va vd 0.1 f agnd agnd 52 40 lpflt 39 ainl+ ainl- ainr+ ainr- 15 16 14 13 connect dgnd and agnd at single point near codec 0.01 f 0.1 f + 10 f +5 v 0.01 f 0.01 f +3.3 v to +5 v + 10 f 0.1 f 0.01 f vls 0.1 f +2.5 v to +5 v 53 vlc 0.1 f +1.8 v to +5 v 6 3 60 59 62 1 64 61 2 63 8 7 scl/cclk sda/cdout ad1/cdin rst 12 9 omck cx_sdin1 sai_lrck sai_sclk cx_sdin3 cx_sdin2 cx_sdin4 cx_lrck cx_sclk ad0/cs 10 int 11 digital audio processor micro- controller 55 rmck 58 adcin1 57 adcin2 cs5361 a/d converter cs5361 a/d converter 56 cx_sdout 54 sai_sdout 48 46 49 44 45 47 rxp0 rxp1/gpo1 s/pdif interface 50 txp driver up to 8 sources 43 rxp2/gpo2 rxp3/gpo3 rxp4/gpo4 rxp5/gpo5 rxp6/gpo6 rxp7/gpo7 42 osc analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) analog output buffer 2 and mute circuit (optional) mute drive (optional) +va * * pull up or down as required on startup if the mute control is used. * 2700 pf* 2700 pf* left analog input right analog inpu analog input buffer 1 analog input buffer 1 cfilt 3 rfilt 3 crip 3 2 k ? 2 k ? ** ** ** resistors are required for i 2 c control port operation 1. see the adc input filter section in the appendix. 2. see the dac output filter section in the appendix. 3. see the pll filter section in the appendix. figure 5. typical connection diagram cs42528
ds586pp5 21 cs42528 4. applications 4.1 overview the cs42528 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital con- verters (adc), implemented using multi-bit delta-sigm a techniques, 8 digital-to-analog converters (dac) and a 192 khz digital audio s/pdif receiver. other f unctions integrated within the codec include indepen- dent digital volume controls for each dac, digital de-emphasis filters for dac and s/pdif, digital gain control for adc channels, adc high-pass filters, an on-chip voltage reference, and an 8:2 mux for s/pdif sources. all serial data is transmitted through two configurable serial audio interfaces with standard serial interface support as well as enhanced one line modes of operation allowing up to 6 channels of serial au- dio data on one data line. all functions are configured through a serial control port operable in spi mode or in i 2 c mode. figure 5 show the recommended connections for the cs42528. the cs42528 operates in one of three oversampling modes based on the input sample rate. mode selec- tion is determined by the fm bits in register ? functional mode (address 03h)? on page 49. single-speed mode (ssm) supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double- speed mode (dsm) supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode (qsm) supports input sample rates up to 192 khz and uses an oversampling ratio of 32x. using the receiver clock recovery pll, a low jitte r clock is recovered from the incoming s/pdif data stream. the recovered clock or an externally supplied clock attached to the omck pin can be used as the system clock. 4.2 analog inputs 4.2.1 line level inputs ainr+, ainr-, ainl+, and ainl- are the line level differential analog inputs. the analog signal must be externally biased to vq, approximately 2.7 v, before being applied to these inputs. the level of the signal can be adjusted for the left and right adc independently through the adc left and right channel gain control registers on page 62. the adc output data is in 2?s complement binary format. for inputs above positive full scale or below negative full scale, the adc will output 7fffffh or 800000h, respectively and cause the adc overflow bit in the register ?inter rupt status (address 20h) (read only)? on page 64 to be set to a ?1?. the rxp/gpo pins may also be configur ed to indicate an overflow condition has occurred in the adc. see ?rxp/general purpose pin control (addresses 29h to 2fh)? on page 70 for proper config- uration. figure 6 shows the full-scale analog input levels. see ?adc input filter? on page 76 for a recom- mended input buffer. ain+ ain- full-scale input level= (ain+) - (ain-)= 5.6 vpp 4.1 v 2.7 v 1.3 v 4.1 v 2.7 v 1.3 v figure 6. full-scale analog input
cs42528 22 ds586pp5 4.2.2 high pass filter an d dc offset calibration the high pass filter continuously subtracts a measure of the dc offset from the output of the decimation filter. the high pass filter can be independently enabl ed and disabled. if the hpf_freeze bit is set during normal operation, the current value of the dc offset for the corresponding channel is frozen and this dc offset will continue to be subtracted from the conv ersion result. this feature makes it possible to perform a system dc offset calibration by: 1) running the cs42528 with the high pass filter enabled until the filter settles. see the digital filter characteristics for filter settling time. 2) disabling the high pass filter and freezing the stored dc offset. the high pass filters are controlled using the hpf_freeze bit in the register ?misc control (address 05h)? on page 52. 4.3 analog outputs 4.3.1 line level outputs and filtering the cs42528 contains on-chip buffer amplifiers capable of producing line level differential outputs. these amplifiers are biased to a quiesc ent dc level of approximately vq. the delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. the remaining out-of-band noise can be attenuated using an off-chip low pass filter. see ?dac output filter? on page 76 for a recommended output buffer. this filter configuration accounts for the normally differing ac loads on the aout+ and aout- differential output pins. it also shows an ac coupling configuration whic h minimizes the number of required ac coupling ca- pacitors. figure 7 shows the full-scale analog output levels. 4.3.2 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the cs42528 incorpo- rates selectable interpolation filters for each mode of oper ation. a ?fast? and a ?slow? roll-off filter is avail- able in single, double, and quad speed modes. the se filters have been designed to accommodate a variety of musical tastes and styles. the filt_sel bit found in the register ?misc control (address 05h)? on page 52 selects which filter is used. filter response plots can be found in figures 45 to 68. aout+ aout- full-scale output level= (ain+) - (ain-)= 5 vpp 3.95 v 2.7 v 1.45 v 3.95 v 2.7 v 1.45 v figure 7. full-scale output
ds586pp5 23 cs42528 4.3.3 digital volume and mute control each dac?s output level is controlled via the volume control registers operating over the range of 0 to -127 db attenuation with 0.5 db resolution. see ?volume control (addresses 0fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)? on page 59. volume control changes are programmable to ramp in increments of 0.125 db at the rate controlled by the szc[1:0] bits in the digital volume control register. see ?volume transition control (address 0dh)? on page 57. each output can be independently muted via mute contro l bits in the register ?channel mute (address 0eh)? on page 59. when enabled, each xx_mute bit attenuates the corresponding dac to its maximum value (-127 db). when the xx_mute bit is disabled, the corresponding dac returns to the attenuation level set in the volume control register. the attenuation is ramped up and down at the rate specified by the szc[1:0] bits. the mute control pin, mutec, is typically connected to an external mute control circuit. the mute control pin outputs high impedance during power up or in powe r down mode by setting the pdn bit in the register ?power control (address 02h)? on page 48 to a ?1?. once out of power-down mode the pin can be con- trolled by the user via the control port, or automatical ly asserted high when zero data is present on all dac inputs, or when serial port clock erro rs are present. to prevent large trans ients on the output, it is desirable to mute the dac outputs before the mute control pin is asserted. please see the mutec pin in the pin descriptions section for more information. each of the rxp1/gpo1-rxp7/gpo7 can be programm ed to provide a hardware mute signal to indi- vidual circuits. when not used as an s/pdif input, each pin can be programmed as an output, with spe- cific muting capabilities as defined by the function bits in the register ?rxp/general purpose pin control (addresses 29h to 2fh)? on page 70. 4.3.4 atapi specification the cs42528 implements the channel mixing functi ons of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 16 on page 61 and figure 8 for additional infor- mation. ? a channel volume control aoutax aoutbx left channel audio data right channel audio data bchannel volume control mute mute cx_sdinx figure 8. atapi block diagram (x = channel pair 1, 2, 3, 4)
cs42528 24 ds586pp5 4.4 s/pdif receiver the cs42528 includes an s/pdif digital audio receiver . the s/pdif receiver accepts and decodes digital audio data according to the iec60958 (s/pdif), and eiaj cp-1201 interface standards. the receiver con- sists of an 8:2 multiplexer input stage driven through pins rxp0 and rxp1/gpo1 - rxp7/gpo7, a pll based clock recovery circuit, and a decoder which sepa rates the audio data from the channel status and user data. a comprehensive buffering scheme provides read access to the channel status and user data. external components are used to terminate and is olate the incoming data cables from the cs42528. these components and required circuitry are detailed in the cdb42528. 4.4.1 8:2 s/pdif input multiplexer the cs42528 contains an 8:2 s/pdif input multiplexer to accommodate up to eight channels of input dig- ital audio data. digital audio data is single-ended and input through the rxp0 and rxp1/gpo1-rxp7/gpo7 pins. any one of these inputs can be multiplexed to the input of the s/pdif receiver and to the s/pdif output pin txp. when any portion of the multiplexer is implement ed, unused rxp0 and rxpx/gpox pins should be tied to a 0.01uf capacitor to ground. the receiver multiplexer select line control is accessed through bits rmux2:0 in the receiver mode control 2 register on page 63. the txp multiplexer select line control is accessed through bits tmux2:0 in the same register. the multiplexer defaults to rxp0 for both functions. 4.4.2 error reporting and hold function while decoding the incoming s/pdif data stream, the cs42528 can identify several kinds of error, indi- cated in the register ?receiver errors (address 26h) (read only)? on page 68. see ?error reporting and hold function? on page 77 for more information. 4.4.3 channel status data handling the first 2 bytes of the channel status block (c data) are decoded into the receiver channel status reg- ister (see ?receiver channel status (address 25h) (read only)? on page 67). see ?channel status data handling? on page 77 for more information. 4.4.4 user data handling the incoming user (u) data is buffered in a user a ccessible buffer. if the u data bits have been encoded as q-channel subcode, the data is decoded and present ed in 10 consecutive register locations, address 30h to 39h. the user can configure the interrupt mask register to cause interrupts to indicate the decod- ing of a new q-channel block, which may be read thr ough the control port. see ?user (u) data e buffer access? on page 79 for more information. 4.4.5 non-audio auto-detection an s/pdif data stream may be used to convey non-audio data, thus it is important to know whether the incoming data stream is digital pcm audio samples or not. this information is typically conveyed in chan- nel status bit 1 (audio ), which is extracted automatically by the cs42528. certain non-audio sources, however, such as ac-3 ? or mpeg encoders, may not adhere to this convention, and the bit may not be properly set. see ?non-audio auto-detection? on page 79 for more information including details for inter- face format detection.
ds586pp5 25 cs42528 4.5 clock generation the clock generation for the cs42528 is shown in the figure below. the internal mclk is derived from the output of the pll or a master clock source attach ed to omck. the mux selection is controlled by the sw_ctrlx bits and can be configur ed to manual switch mode only, or automatically switch on loss of pll lock to the other source input. 4.5.1 pll and jitter attenuation an on-chip phase locked loop (pll) is used to reco ver the clock from the incoming s/pdif data stream. there are some applications where low jitter in the re covered clock, presented on the rmck pin, is im- portant. for this reason, the pll has been designed to have good jitter attenuation characteristics as shown in figure 28 on page 81. the pll can be configured to lock onto the incoming sai_lrck signal from the serial audio interface port and generate the required internal master clock frequency. by setting the pll_lrck bit to a ?1? in the register ?clock control (address 06h)? on page 53, the pll will lock to the incoming sai_lrck and generate an output master clock (rmck) of 256fs. table 2 shows the output of the pll with typical input fs values for sai_lrck. see ?appendix c: pll filter? on page 80 for more inform ation concerning pll operation, required filter components, optimal layout guidelines and jitter attenuation characteristics. sai_lrck (slave mode) recovered s/pdif clock 0 1 pll (256fs) 8.192 - 49.152 mhz 00 01 pll_lrck bit sw_ctrlx bits (manual or auto switch) omck auto detect input clock 1,1.5, 2, 4 single speed 256 double speed 128 quad speed 64 single speed 4 double speed 2 quad speed 1 00 01 10 00 01 10 00 01 10 00 01 10 not olm olm #1 codec_fmx bits sai_fmx bits dac_olx or adc_olx bits adc_olx and adc_sp selx bits sai_sclk cx_sclk cx_lrck sai_lrck rmck olm #2 not olm olm #1 olm #2 128fs 256fs 128fs 256fs internal mclk 00 01 10 11 rmck_divx bits 2 4 x2 figure 9. cs42528 clock generation
cs42528 26 ds586pp5 4.5.2 omck system clock mode a special clock switching mode is avai lable that allows the clock that is input through the omck pin to be used as the internal master clock. this feature is cont rolled by the sw_ctrlx bits in register ?clock con- trol (address 06h)? on page 53. an advanced auto switching mode is also implemented to maintain master clock functionality. the clock auto sw itching mode allows the clock input through omck to be used as a clock in the system without any disruption when the pll loses lock; for example, when the input is re- moved from the receiver. this clock switching is d one glitch free. a clock adhering to the specifications detailed in the switching characteristics table on page 12 must be applied to the omck pin at all times that the frc_pll_lk bit is set to ?0? (see ?force pll lock (frc_pll_lk)? on page 54). 4.5.3 master mode in master mode, the serial interface timings are der ived from an external clock attached to omck or the output of the pll with an input reference to either the s/pdif receiver recovered clock or the sai_lrck input from the serial audio interface port. master clock selection and operation is configured with the sw_ctrl1:0 bits in the clock control register (see ?clock control (address 06h)? on page 53). the supported pll output frequencies are shown in table 2 below. 4.5.4 slave mode in slave mode, cx_lrck, cx_sclk and/or sai_lrck, sai_sclk operate as inputs. the left/right clock signal must be equal to the sample rate, fs , and must be synchronously derived from the supplied master clock, omck or the output of the pll. the serial bit clock, cx_sclk and/or sai_sclk, must be synchronously derived from the master clock and be equ al to 128x, 64x, 48x or 32x fs depending on the interface format selected and desired speed mode. one line mode #1 is supported in slave mode. one line mode #2 is not supported. refer to table 3 for requi red clock ratios. the sample rate to omck ratios and omck frequency requirements for slave mode operation are shown in table 1. single speed double speed quad speed one line mode #1 omck/lrck ratio 256x, 384x, 512x 128x, 192x, 256x 64x, 96x, 128x 256x table 3. slave mode clock ratios sample rate (khz) omck (mhz) single speed (4 to 50 khz) double speed (50 to 100 khz) quad speed (100 to 192 khz) 256x 384x 512x 128x 192x 256x 64x 96x 128x 48 12.2880 18.4320 24.5760 - - - - - - 96 - - - 12.2880 18.4320 24.5760 - - - 192 - - - - - - 12.2880 18.4320 24.5760 table 1. common omck clock frequencies sample rate (khz) pll output (mhz) single speed (4 to 50 khz) double speed (50 to 100 khz) quad speed (100 to 192 khz) 256x 256x 256x 32 8.1920 - - 44.1 11.2896 - - 48 12.2880 - - 64 - 16.3840 - 88.2 - 22.5792 - 96 - 24.5760 - 176.4 - - 45.1584 192 - - 49.1520 table 2. common pll output clock frequencies
ds586pp5 27 cs42528 4.6 digital interfaces 4.6.1 serial audio interface signals the cs42528 interfaces to an external digital a udio processor via two independent serial ports, the codec serial port, codec_sp and the serial audio inte rface serial port, sai_sp. the digital output of the internal adcs can be configur ed to use either the cx_sdout pin or the sai_sdout pin and the corresponding serial port clocking signals. these config uration bits and the selection of single, double or quad-speed mode for codec_sp and sai_sp are found in register ?functional mode (address 03h)? on page 49. the serial interface clocks, sai_sclk for sai_sp and cx_sclk for codec_sp, are used for transmit- ting and receiving audio data. either sai_sclk or cx_sclk can be generated by the cs42528 (master mode) or it can be input from an external source (slave mode). master or sl ave mode selection is made using bits codec_sp m/s and sai_sp m/s in register ?misc control (address 05h)? on page 52. the left/right clock (sai_lrck or cx_lrck) is used to indicate left and right data frames and the start of a new sample period. it may be an output of the cs42528 (master mode), or it may be generated by an external source (slave mode). as described in la ter sections, particular modes of operation do allow the sample rate, fs, of the sai_sp and the codec_sp to be different, but must be multiples of each other. the serial data interface format selection (left/right justified, i 2 s or one line mode) for the serial audio in- terface serial port data out pin, sai_sdout, the co dec serial port data out pin, cx_sdout, and the codec input pins, cx_sdin1:4, is c onfigured using the appropriate bits in the register ?interface for- mats (address 04h)? on page 50. the serial audio data is presented in 2's complement binary form with the msb first in all formats. cx_sdin1, cx_sdin2, cx_sdin3 and cx_sdin4 are t he serial data input pins supplying the associat- ed internal dac. cx_sdout, the adc data output pi n, carries data from the two internal 24-bit adcs and, when configured for one-line mode, up to four additional adc channels attached externally to the signals adcin1 and adcin2 (typically two cs5361 stereo adcs). when operated in one line mode, 6 channels of dac data are input on cx_sdin1, two additional dac channels on cx_sdin4, and 6 chan- nels of adc data are output on cx_sdout. table 4 outlines the serial port channel allocations. sclk/lrck ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x 128x serial inputs / outputs cx_sdin1 left channel right channel one line mode dac #1 dac #2 dac channels 1,2,3,4,5,6 cx_sdin2 left channel right channel one line mode dac #3 dac #4 not used cx_sdin3 left channel right channel one line mode dac #5 dac #6 not used table 4. serial audio port channel allocations single speed double speed quad speed one line mode #1 table 3. slave mode clock ratios
cs42528 28 ds586pp5 cx_sdin4 left channel right channel one line mode dac #7 dac #8 dac channels 7,8 cx_sdout left channel right channel one line mode adc #1 adc #2 adc channels 1,2,3,4,5,6 sai_sdout left channel right channel one line mode s/pdif left or adc #1 s/pdif right or adc #2 adc channels 1,2,3,4,5,6 adcin1 left channel right channel external adc #3 external adc #4 adcin2 left channel right channel external adc #5 external adc #6 serial inputs / outputs table 4. serial audio port channel allocations
ds586pp5 29 cs42528 4.6.2 serial audio interface formats the codec_sp and sai_sp digital audio serial ports support 5 formats with varying bit depths from 16 to 24 as shown in figures 10 to 14. these formats are selected using the configurat ion bits in the registers, ?functional mode (address 03h)? on page 49 and ?int erface formats (address 04h)? on page 50. for the diagrams below, single-speed mode is equivalent to fs = 32, 44. 1, 48 khz; double-speed mode is for fs = 64, 88.2, 96 khz; and quad-speed mode is for fs = 176.4, 196 khz. left channel right channel cx_sdinx cx_sdout sai_sdout +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb cx_lrck sai_lrck cx_sclk sai_sclk figure 10. i 2 s serial audio formats i2s mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 48, 64, 128 fs single-speed mode 64 fs 64 fs double-speed mode 64 fs 64 fs quad-speed mode 18 to 24 64, 128, 256 fs 48, 64, 128 fs single-speed mode 64 fs 48, 64 fs double-speed mode 64 fs 48, 64 fs quad-speed mode
cs42528 30 ds586pp5 cx_lrck sai_lrck cx_sclk sai_sclk left channel right channel cx_sdinx cx_sdout sai_sdout +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 11. left justified serial audio formats left justified mode, data va lid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 32, 48, 64, 128 fs single-speed mode 64 fs 32, 64 fs double-speed mode 64 fs 32, 64 fs quad-speed mode 18 to 24 64, 128, 256 fs 48, 64, 128 fs single-speed mode 64 fs 48, 64 fs double-speed mode 64 fs 48, 64 fs quad-speed mode left channel right channel 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 cx_sdinx cx_sdout sai_sdout cx_lrck sai_lrck cx_sclk sai_sclk figure 12. right justified serial audio formats right justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 16 64 32, 48, 64, 128 fs single-speed mode 64 fs 32, 64 fs double-speed mode 64 fs 32, 64 fs quad-speed mode 24 64, 128, 256 fs 48, 64, 128 fs single-speed mode 64 fs 48, 64 fs double-speed mode 64 fs 48, 64 fs quad-speed mode
ds586pp5 31 cs42528 figure 13. one line mode #1 serial audio format one line data mode #1, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 20 128 fs 128 fs single-speed mode 128 fs 128 fs double-speed mode cx_lrck sai_lrck cx_sclk sai_sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac1 dac3 dac5 dac2 dac4 dac6 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel 20 clks dac7 dac8 20 clks cx_sdin4 20 clks adc1 adc3 adc5 adc2 adc4 adc6 20 clks 20 clks 20 clks 20 clks 20 clks cx_sdout sai_sdout cx_sdin1 lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac1 dac3 dac5 dac2 dac4 dac6 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 24 clks dac7 dac8 24 clks 24 clks adc1 adc3 adc5 adc2 adc4 adc6 24 clks 24 clks 24 clks 24 clks 24 clks 128 clks cx_lrck sai_lrck cx_sclk sai_sclk cx_sdout sai_sdout cx_sdin1 cx_sdin4 figure 14. one line mode #2 serial audio format one line data mode #2, data valid on rising edge of sclk bits/sample sclk rate(s) notes master slave 24 256 fs not supported single-speed mode
cs42528 32 ds586pp5 4.6.3 adcin1/adcin2 serial data format the two serial data lines which interface to the optional external adcs, adcin1 and adcin2, support only left-justified, 24-bit samples at 64fs or 128fs. this interface is not affected by any of the serial port configuration register bit setti ngs. these serial data lines are us ed when supporting one line mode of operation with external adcs attached. if these si gnals are not being used, they should be tied together and wired to gnd via a pull-down resistor. for proper operation, the cs42528 must be configured to select which sclk/lrck is being used to clock the external adcs. the ext adc sclk bit in regi ster ?misc control (address 05h)? on page 52, must be set accordingly. set this bit to ?1? if the external adcs are wired using the codec_sp clocks. if the adcs are wired to use the sai_sp clocks, set this bit to ?0?. cx_lrck sai_lrck cx_sclk sai_sclk left channel right channel adcin1/2 +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 15. adcin1/adcin2 serial audio format left justified mode, data valid on rising edge of sclk bits/sample sclk rate(s) notes 24 64, 128 fs single-speed mode, fs= 32, 44.1, 48 khz 64 fs double-speed mode, fs= 64, 88.2, 96 khz not supported quad-speed mode, fs= 176.4, 192 khz
ds586pp5 33 cs42528 4.6.4 one line mode (olm) configurations 4.6.4a olm config #1 one line mode configuration #1 can support up to 8 ch annels of dac data, 6 channels of adc data and 2 channels of s/pdif received data. this is the only c onfiguration which will support up to 24-bit samples at a sampling frequency of 48 khz on all channels for both the dac and adc. register / bit settings description functional mode register (addr = 03h) set codec_fmx = sai_fmx = 00,01,10 cx_lrck must equal sai_lrck; sample rate conversion not supported set adc_sp selx = 00 configure adc data on cx_sdout, s/pdif data on sai_sdout interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one line mode set adc_olx bits = 00,01,10 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01,10 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set codec_sp m/s = 1 configure codec serial port to master mode. set sai_sp m/s = 1 configure serial audio interface port to master mode. set ext adc sclk = 0 identify external adc clock source as sai serial port. dac mode not one line mode one line mode #1 one line mode #2 adc mode not one line mode cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=64 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=64 fs sai_lrck=cx_lrck not valid one line mode #1 cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=64 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=64 fs sai_lrck=cx_lrck not valid one line mode #2 cx_sclk=256 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck not valid cx_sclk=256 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdin_port2 sclk_port3 lrck_port3 sdout1_port3 sdout2_port3 sdout3_port3 sdout4_port3 sai_sclk sai_lrck sai_sdout cx_sclk cx_lrck cx_sdout cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs spdif data adc data 64fs,128fs, 256fs digital audio processor cs5361 cs5361 mclk figure 16. olm configuration #1 cs42528
cs42528 34 ds586pp5 4.6.4b olm config #2 this configuration will support up to 8 channels of dac data, 6 channels of adc data and no channels of s/pdif received data and will handle up to 20-bit samp les at a sampling frequency of 96 khz on all chan- nels for both the dac and adc. the output data stream of the internal and external adcs is configured to use the sai_sdout output and run at the sai_sp clock speeds. register / bit settings description functional mode register (addr = 03h) set codec_fmx = sai_fmx = 00,01,10 cx_lrck must equal sai_lrck; sample rate conversion not supported set adc_sp selx = 10 configure adc data to use sai_sdout and sai_sp clocks. s/pdif data is not supported in this configuration interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one line mode set adc_olx bits = 00,01,10 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set codec_sp m/s = 1 set codec serial port to master mode. set sai_sp m/s = 1 set serial audio interface port to master mode. set ext adc sclk = 1 identify external adc clock s ource as codec serial port. cx_sdout= not used sai_sdout=adc data dac mode not one line mode one line mode #1 one line mode #2 adc mode not one line mode cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=64 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck not valid one line mode #1 cx_sclk=64 fs cx_lrck=ssm/dsm sai_sclk=128 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm sai_sclk=128 fs sai_lrck=cx_lrck not valid one line mode #2 cx_sclk=64 fs cx_lrck=ssm sai_sclk=256 fs sai_lrck=cx_lrck not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdin_port2 sclk_port3 lrck_port3 sdout1_port3 sdout2_port3 sdout3_port3 sdout4_port3 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs,128fs adc data 64fs,128fs, 256fs digital audio processor cs5361 cs5361 sai_sclk sai_lrck sai_sdout cx_sclk cx_lrck cx_sdout cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 mclk figure 17. olm configuration #2 cs42528
ds586pp5 35 cs42528 4.6.4c olm config #3 this one line mode configuration #3 will support up to 8 channels of dac data, 6 channels of adc data and 2 channels of s/pdif received data and will h andle up to 20-bit samples at a sampling frequency of 48 khz on all channels for both the dac and adc. the output data stream of the internal and external adcs is configured to use the cx_sdout output and run at the codec_sp clock speeds. one line mode #2, which supports 24-bit samples, is not supported by this configuration. register / bit settings description functional mode register (addr = 03h) set codec_fmx = sai_fmx = 00,01,10 cx_lrck must equal sai_lrck; sample rate conversion not supported set adc_sp selx = 00 configure adc data to use cx_sdout and codec_sp clocks. s/pdif data is supported on sai_sdout interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one line mode set adc_olx bits = 00,01 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set codec_sp m/s = 1 set codec serial port to master mode. set sai_sp m/s = 0 or 1 set serial audio interface port to master mode or slave mode. set ext adc sclk = 1 identify external adc clock s ource as codec serial port. cx_sdout= adc data sai_sdout=s/pdif data dac mode not one line mode one line mode #1 one line mode #2 adc mode not one line mode cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=64 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck not valid one line mode #1 cx_sclk=128 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck cx_sclk=128 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=cx_lrck not valid one line mode #2 not valid not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdin_port2 sclk_port3 lrck_port3 sdout1_port3 sdout2_port3 sdout3_port3 sdout4_port3 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs spdif data adc data 64fs,128fs digital audio processor cs5361 cs5361 sai_sclk sai_lrck sai_sdout cx_sclk cx_lrck cx_sdout cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 mclk figure 18. olm configuration #3 cs42528
cs42528 36 ds586pp5 4.6.4d olm config #4 this configuration will support up to 8 channels of dac data, 6 channels of adc data and no channels of s/pdif received data. olm config #4 will handle up to 20-bit adc samples at an fs of 48 khz and 24-bit dac samples at an fs of 48 khz. since the adcs data stream is configured to use the sai_sdout out- put and the internal and external adcs are clocked from the sai_sp, then the sample rate for the codec serial port can be different from the sample rate of the serial audio interfac e serial port. register / bit settings description functional mode register (addr = 03h) set codec_fmx = 00,01,10 cx_lrck can run at ssm, dsm, or qsm independent of sai_lrck set sai_fmx = 00,01,10 sai_lrck can run at ssm, dsm, or qsm independent of cx_lrck set adc_sp selx = 10 configure adc data to use sai_sdout and sai_sp clocks. s/pdif data is not supported in this configuration interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one line mode set adc_olx bits = 00,01 select adc operating mode, see table below for valid combinations set dac_olx bits = 00,01,10 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set codec_sp m/s = 1 set dac serial port to master mode. set sai_sp m/s = 0 or 1 set adc serial port to master mode or slave mode. set ext adc sclk = 0 identify external adc clock source as sai serial port. cx_sdout= not used sai_sdout=adc data dac mode not one line mode one line mode #1 one line mode #2 adc mode not one line mode cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=64 fs sai_lrck=ssm/dsm/qsm cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=64 fs sai_lrck=ssm/dsm/qsm cx_sclk=256 fs cx_lrck=ssm sai_sclk=64 fs sai_lrck=ssm/dsm/qsm one line mode #1 cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=128 fs sai_lrck=ssm cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=128 fs sai_lrck=ssm cx_sclk=256 fs cx_lrck=ssm sai_sclk=128 fs sai_lrck=ssm one line mode #2 not valid not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdin_port2 sclk_port3 lrck_port3 sdout1_port3 sdout2_port3 sdout3_port3 sdout4_port3 rmck adcin1 adcin2 mclk sdout1 sdout2 lrck sclk 64fs,128fs,256fs adc data 64fs,128fs digital audio processor cs5361 cs5361 sai_sclk sai_lrck sai_sdout cx_sclk cx_lrck cx_sdout cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 mclk figure 19. olm configuration #4 cs42528
ds586pp5 37 cs42528 4.6.4e olm config #5 this one-line mode configuration can support up to 8 channels of dac data, 2 channels of adc data and 2 channels of s/pdif received data and will h andle up to 24-bit samples at a sampling frequency of 48 khz on all channels for both the dac and adc. the output data stream of the internal adcs can be configured to use the cx_sdout output and run at the codec_sp clock speeds or to use the sai_sdout data output and run at the sai_sp rate. the codec_sp and sai_sp can operate at differ- ent fs rates. register / bit settings description functional mode register (addr = 03h) set codec_fmx = 00,01,10 cx_lrck can run at ssm, dsm, or qsm independent of sai_lrck set sai_fmx = 00,01,10 sai_lrck can run at ssm, dsm, or qsm independent of cx_lrck set adc_sp selx = 00,01,10 configure adc data to use cx_sdout and codec_sp clocks, or sai_sdout and sai_sp cocks. interface format register (addr = 04h) set difx bits to proper serial format select the digital interface format when not in one line mode set adc_olx bits = 00 set adc operating mode to not one line mode since only 2 channels of adc are supported set dac_olx bits = 00,01 select dac operating mode, see table below for valid combinations misc. control register (addr = 05h) set codec_sp m/s = 0 or 1 set codec serial port to master mode or slave mode. set sai_sp m/s = 0 or 1 set serial audio interface port to master mode or slave mode. set ext adc sclk = 0 external adcs are not used. leave bit in default state. cx_sdout= adc data sai_sdout=adc or s/pdif data dac mode not one line mode one line mode #1 one line mode #2 adc mode not one line mode cx_sclk=64 fs cx_lrck=ssm/dsm/qsm sai_sclk=64 fs sai_lrck=ssm/dsm/qsm cx_sclk=128 fs cx_lrck=ssm/dsm sai_sclk=64 fs sai_lrck=ssm/dsm/qsm not valid one line mode #1 not valid not valid not valid one line mode #2 not valid not valid not valid sclk_port1 lrck_port1 sdin_port1 sclk_port2 lrck_port2 sdin_port2 sclk_port3 lrck_port3 sdout1_port3 sdout2_port3 sdout3_port3 sdout4_port3 rmck adcin1 adcin2 spdif or adc data adc data 64fs,128fs, 256fs digital audio processor sai_sclk sai_lrck sai_sdout cx_sclk cx_lrck cx_sdout cx_sdin1 cx_sdin2 cx_sdin3 cx_sdin4 64fs,128fs, 256fs mclk figure 20. olm configuration #5 cs42528
cs42528 38 ds586pp5 4.7 control port d escription and timing the control port is used to access the registers, allowing the cs42528 to be configured for the desired operational modes and formats. the operation of the control port may be completely asynchronous with respect to the audio sample rates. however, to avoi d potential interference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i 2 c, with the cs42528 acting as a slave device. spi mode is se- lected if there is a high to low transition on the ad0/cs pin, after the rst pin has been brought high. i 2 c mode is selected by connecting the ad0/cs pin through a resistor to vlc or dgnd, thereby permanently selecting the desired ad0 bit address state. 4.7.1 spi mode in spi mode, cs is the cs42528 chip select signal, cclk is the control port bit clock (input into the cs42528 from the microcontroller), cdin is the inpu t data line from the microcontroller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 21 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 1001111. the eighth bit is a read/write indi- cator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the register designated by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto increment capabilit y, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or wr ites. if incr is set to a 1, the map will autoincrement after each byte is read or written, allowing bl ock reads or writes of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecutively. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 1001111 1001111 map = memory address pointer, 8 bits, msb first high impedance figure 21. control port timing in spi mode
ds586pp5 39 cs42528 4.7.2 i 2 c mode in i 2 c mode, sda is a bidirectional data line. data is cl ocked into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least si gnificant bits of the chip address and should be connected through a resistor to vlc or dgnd as desired. the state of the pins is sensed while the cs42528 is being reset. the signal timings for a read and write cycle are sh own in figure 22 and figure 23. a start condition is defined as a falling transition of sda while the clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs42528 after a start condition consists of a 7 bit chip address field and a r/w bit (high for a read, low for a write). the upper 5 bits of the 7-bit address field are fixed at 10011. to communicate with a cs42528, the chip address field, which is the first byte s ent to the cs42528, should match 10011 followed by the settings of the ad1 and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the op- eration is a read, the contents of the register pointed to by the map will be output. setting the auto incre- ment bit in map allows successive r eads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs42528 after each input byte is read, and is input to the cs42528 from the microcontroller after each transmitted byte. since the read operation can not set the map, an aborted write operation is used as a preamble. as shown in figure 23, the write operation is aborted after the acknowledge for the map byte by sending a stop condition. the following pseudocode illustrates an aborted write operation followed by a read oper- ation. send start condition. send 10011xx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 22. control port timing, i 2 c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 ad1 ad0 0 sda 1 0 0 1 1 ad1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 23. control port timing, i 2 c read
cs42528 40 ds586pp5 send stop condition, aborting write. send start condition. send 10011xx1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in the map allows successi ve reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4.8 interrupts the cs42528 has a comprehensive interrupt capability. the int output pin is intended to drive the inter- rupt input pin on the host microcontroller. the int pin may be set to be active low, active high or active low with no active pull-up transistor. this last mode is used for active low, wired-or hook-ups, with mul- tiple peripherals connected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in the interrupt stat us register descriptions. see ?inter- rupt status (address 20h) (read only)? on page 64. each source may be masked off through mask reg- ister bits. in addition, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different con- figurations are possible, depending on the needs of the equipment designer. 4.9 reset and power-up reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. it is also recomme nded that reset be activated if the analog or digital supplies drop below the recommended operating conditi on to prevent power glitch related issues. when rst is low, the cs42528 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. when rst is high, the control port becomes oper- ational and the desired settings shoul d be loaded into the control registers. writing a 0 to the pdn bit in the power control register will then cause the part to leave the low power state and begin operation. if the internal pll is selected as the clock source, th e serial audio outputs will be enabled after the pll has settled. see ?power control (address 02h)? on page 48 for more details. the delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the rst pin high. however, the voltage reference will take much longer to reach a final value due to the presenc e of external capacitance on the filt+ pin. a time delay of approximately 80ms is required after applying power to the device or after exiting a reset state. during this voltage reference ramp delay, all serial ports and dac outputs will be automatically muted. 4.10 power supply, groun ding, and pcb layout as with any high resolution converter, the cs42528 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 5 shows the recommended power arrangements, with va and varx connected to clean suppl ies. vd, which powers the digital circuitry, may be run from the system logic supply. alternatively, vd may be powered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. for applications where the output of the pll is required to be low jitter, use a separate, low noise analog +5 v supply for varx, decoupled to agnd. in addition, a separate region of analog ground plane around the filt+, vq, lpflt, refgnd, agnd, va, varx, rxp/and rxp0 pins is recommended.
ds586pp5 41 cs42528 extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. dec oupling capacitors should be as near to the pins of the cs42528 as possible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the cs42528 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+, vq and lpflt pi ns in order to avoid unwanted coupling into the modulators and pll. the filt+ and vq decoupling capacitors, particularly the 0.1 f, must be positioned to minimize the electrical path from filt+ a nd refgnd. the cdb42528 evaluation board demonstrates the optimum layout and power supply arrangements.
cs42528 42 ds586pp5 5. register quick reference addr function 7 6 5 4 3 2 1 0 01h id chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0 page 47 default 1111xxxx 02h power con- trol pdn_rcvr1 pdn_rcvr0 pdn_adc pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn page 48 default 1000000 1 03h functional mode codec_fm1 codec_fm0 sai_fm1 sai_fm0 adc_sp sel1 adc_sp sel0 dac_dem rcvr_dem page 47 default 0000000 0 04h interface formats dif1 dif0 adc_ol1 adc_ol0 dac_ol1 dac_ol0 sai_rj16 codec_rj16 page 50 default 0100000 0 05h misc control ext adc sclk hiz_rmck reserved freeze filtsel hpf_ freeze codec_sp m/s sai_sp m/s page 52 default 0000000 0 06h clock con- trol rmck_div1 rmck_div0 omck freq1 omck freq0 pll_lrck sw_ctrl1 sw_ctrl0 frc_pll_lk page 53 default 0000000 0 07h omck/pll_ clk ratio ratio7 ratio6 ratio5 ratio4 ratio3 ratio2 ratio1 ratio0 page 55 default xxxxxxx x 08h rvcr sta- tus digital silence aes format2 aes format1 aes format0 active_clk rvcr_clk2 rvcr_clk1 rvcr_clk0 page 55 default xxxxxxx x 09h burst pre- amble pc byte 0 pc0-7 pc0-6 pc0-5 pc0-4 pc0-3 pc0-2 pc0-1 pc0-0 page 56 default xxxxxxx x 0ah burst pre- amble pc byte 1 pc1-7 pc1-6 pc1-5 pc1-4 pc1-3 pc1-2 pc1-1 pc1-0 page 56 default xxxxxxx x 0bh burst pre- amble pd byte 0 pd0-7 pd0-6 pd0-5 pd0-4 pd0-3 pd0-2 pd0-1 pd0-0 page 56 default xxxxxxx x 0ch burst pre- amble pd byte 1 pd1-7 pd1-6 pd1-5 pd1-4 pd1-3 pd1-2 pd1-1 pd1-0 page 56 default xxxxxxx x 0dh volume control reserved sngvol szc1 szc0 amute mute sai_sp ramp_up ramp_dn page 57 default 0000100 0
ds586pp5 43 cs42528 0eh channel mute b4_mute a4_mute b3_mute a3_mute b2_mute a2_mute b1_mute a1_mute page 59 default 0000000 0 0fh vol. control a1 a1_vol7 a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 page 59 default 0000000 0 10h vol. control b1 b1_vol7 b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 page 59 default 0000000 0 11h vol. control a2 a2_vol7 a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 page 59 default 0000000 0 12h vol. control b2 b2_vol7 b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 page 59 default 0000000 0 13h vol. control a3 a3_vol7 a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 page 59 default 0000000 0 14h vol. control b3 b3_vol7 b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 page 59 default 0000000 0 15h vol. control a4 a4_vol7 a4_vol6 a4_vol5 a4_vol4 a4_vol3 a4_vol2 a4_vol1 a4_vol0 page 59 default 0000000 0 16h vol. control b4 b4_vol7 b4_vol6 b4_vol5 b4_vol4 b4_vol3 b4_vol2 b4_vol1 b4_vol0 page 59 default 0000000 0 17h channel invert inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 page 59 default 0000000 0 18h mixing ctrl pair 1 p1_a=b reserved reserved p1_atapi4 p1_atapi3 p1_atapi2 p1_atapi1 p1_atapi0 page 60 default 0000100 1 19h mixing ctrl pair 2 p2_a=b reserved reserved p2_atapi4 p2_atapi3 p2_atapi2 p2_atapi1 p2_atapi0 page 60 default 0000100 1 1ah mixing ctrl pair 3 p3_a=b reserved reserved p3_atapi4 p3_atapi3 p3_atapi2 p3_atapi1 p3_atapi0 page 60 default 0000100 1 1bh mixing ctrl pair 4 p4_a=b reserved reserved p4_atapi4 p4_atapi3 p4_atapi2 p4_atapi1 p4_atapi0 page 60 default 0000100 1 addr function 7 6 5 4 3 2 1 0
cs42528 44 ds586pp5 1ch adc left ch. gain reserved reserved lgain5 lgain4 lgain3 lgain2 lgain1 lgain0 page 62 default 0000000 0 1dh adc right ch. gain reserved reserved rgain5 rgain4 rgain3 rgain2 rgain1 rgain0 page 62 default 0000000 0 1eh rcvr mode ctrl sp_sync reserved de-emph1 de-emph0 int1 int0 hold1 hold0 page 62 default 0000000 0 1fh rcvr mode ctrl 2 reserved tmux2 tmux1 tmux0 reserved rmux2 rmux1 rmux0 page 63 default 0000000 0 20h interrupt status unlock reserved qch detc detu reserved overflow rerr page 64 default xxxxxxx x 21h interrupt mask unlockm reserved qchm detcm detum reserved overflowm rerrm page 65 default 0000000 0 22h interrupt mode msb unlock1 reserved qch1 detc1 detu1 reserved of1 rerr1 page 65 default 0000000 0 23h interrupt mode lsb unlock0 reserved qch0 detc0 detu0 reserved of0 rerr0 page 65 default 0000000 0 24h buffer ctrl reserved lockm reserved reserved reserved bsel cam chs page 66 default 0100000 0 25h rcvr cs data aux3 aux2 aux1 aux0 pro audio copy orig page 67 default 0000000 0 26h rcvr errors reserved qcrc ccrc unlock v conf bip par page 68 default 0000000 0 27h rcvr errors mask reserved qcrcm ccrcm unlockm vm confm bipm parm page 69 default 0000000 0 28h mutec reserved reserved mcpolarity m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 page 69 default 0001111 1 29h rxp7/gpo 7 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 addr function 7 6 5 4 3 2 1 0
ds586pp5 45 cs42528 2ah rxp6/gpo 6 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 2bh rxp5/gpo 5 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 2ch rxp4/gpo 4 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 2dh rxp3/gpo 3 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 2eh rxp2/gpo 2 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 2fh rxp1/gpo 1 mode1 mode0 polarity function4 function3 function2 function1 function0 page 70 default 0000000 0 30h q subcode address3 address2 address1 address0 control3 control2 control1 control0 page 72 default xxxxxxx x 31h q subcode track7 track6 track5 tr ack4 track3 track2 track1 track0 page 72 default xxxxxxx x 32h q subcode index7 index6 index 5 index4 index3 index2 index1 index0 page 72 default xxxxxxx x 33h q subcode minute7 minute6 minute5 minute4 minute3 minute2 minute1 minute0 page 72 default xxxxxxx x 34h q subcode second7 second6 second5 second4 second3 second2 second1 second0 page 72 default xxxxxxx x 35h q subcode frame7 frame6 frame5 frame4 frame3 frame2 frame1 frame0 page 72 default xxxxxxx x 36h q subcode zero7 zero6 zero5 zero4 zero3 zero2 zero1 zero0 page 72 default xxxxxxx x 37h q subcode a.minute7 a.minute6 a.minute5 a.mi nute4 a.minute3 a.minute2 a.minute1 a.minute0 page 72 default xxxxxxx x 38h q subcode a.second7 a.second6 a.second5 a.s econd4 a.second3 a.second2 a.second1 a.second0 page 72 default xxxxxxx x 39h q subcode a.frame7 a.frame6 a.frame5 a.frame4 a.frame3 a.frame2 a.frame1 a.frame0 page 72 default xxxxxxx x addr function 7 6 5 4 3 2 1 0
cs42528 46 ds586pp5 3ah - c or u data buffer cu buffer7 cu buffer6 cu buffer5 cu buffer4 cu buffer3 cu buffer2 cu buffer1 cu buffer0 51h page 72 default xxxxxxx x addr function 7 6 5 4 3 2 1 0
ds586pp5 47 cs42528 6. register description all registers are read/write except for the i.d. and revision register, omck/pl l_clk ratio register, in- terrupt status register, and q-c hannel subcode bytes and c-bit or u-bit data buffer, which are read only. see the following bit definition tables for bit assignment information. the default state of each bit after a power-up sequence or reset is listed in each bit description. 6.1 memory address pointer (map) not a register 6.1.1 increment(incr) default = 1 function: memory address pointer auto increment control 0 - map is not incremented automatically. 1 - internal map is automatically in cremented after each read or write. 6.1.2 memory addr ess pointer (mapx) default = 0000001 function: memory address pointe r (map). sets the re gister address that will be read or written by the control port. 6.2 chip i.d. and revision register (address 01h) (read only) 6.2.1 chip i.d. (chip_idx) default = 1111 function: i.d. code for the cs42528. permanently set to 1111. 6.2.2 chip revision (rev_idx) default = 0100 function: cs42528 revision level. revision d is coded as 0100. revision c is coded as 0011. 76543210 incr map6 map5 map4 map3 map2 map1 map0 76543210 chip_id3 chip_id2 chip_id1 chip_id0 rev_id3 rev_id2 rev_id1 rev_id0
cs42528 48 ds586pp5 6.3 power control (address 02h) 6.3.1 power down receiver (pdn_rcvrx) default = 10 00 - receiver and pll in normal operational mode. 01 - receiver and pll held in a reset state. equivalent to setting 11. 10 - reserved. 11 - receiver and pll held in a reset state. equivalent to setting 01. function: places the s/pdif receiver and pll in a reset state. it is advised that any change of these bits be made while the dacs are muted or the power down bit (pdn) is en abled to eliminate the possibility of audible artifacts. it should be noted that, for revision c compatib ility, pdn_rcvr1 may be set to ?0? and receiver op- eration may be controlled with the pdn_rcvr0 bit. 6.3.2 power down adc (pdn_adc) default = 0 function: when enabled the stereo analog to di gital converter will remain in a rese t state. it is advised that any change of this bit be made while the dacs are mut ed or the power down bit (pdn) is enabled to elim- inate the possibility of audible artifacts. 6.3.3 power down dac pairs (pdn_dacx) default = 0 function: when enabled the respective dac channel pair x (aoutax and aoutbx) will remain in a reset state. 6.3.4 power down (pdn) default = 1 function: the entire device will enter a low-power state when th is function is enabled, and the conten ts of the control registers are retained in this mode. the power down bit defaults to ?enabled? on power-up and must be disabled before normal operation can occur. 76543210 pdn_rcvr1 pdn_rcvr0 pdn_adc pdn_dac4 pdn_dac3 pdn_dac2 pdn_dac1 pdn
ds586pp5 49 cs42528 6.4 functional mode (address 03h) 6.4.1 codec functional mode (codec_fmx) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 192 khz sample rates) 11 - reserved function: selects the required range of sample rates for all converters clocked from the codec serial port (codec_sp). bits must be set to the corresponding sa mple rate range when th e codec_sp is in master or slave mode. 6.4.2 serial audio interface functional mode (sai_fmx) default = 00 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 192 khz sample rates) 11 - reserved function: selects the required range of sample rates for the serial audio interface port(sai_sp). these bits must be set to the corresponding sample rate ra nge when the sai_sp is in master or slave mode. 6.4.3 adc serial port select (adc_sp selx) default = 00 00 - serial data on cx_sdout pin, clocked fr om the codec_sp. s/pdif data on sai_sdout pin. 01 - serial data on cx_sdout pin, clocked from the sai_sp. s/pdif data on sai_sdout pin. 10 - serial data on sai_sdout pin, clocke d from the sai_sp. no s/pdif data available. 11 - reserved function: selects the desired clocks and routing for the adc serial output. 6.4.4 dac de-emphasis control (dac_dem) default = 0 function: enables the digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 khz. de-e mphasis will not be e nabled, regardless of this register setting, at any other sample rate. if the frc_pll_lk bit is set to a ?1?b, then the auto- detect sample rate feature is disabled. to apply the correct de-emphasis filter, use the de-emph bits 76543210 codec_fm1 codec_fm0 sai_fm1 sai_fm0 adc_sp sel1 adc_sp sel0 dac_dem rcvr_dem
cs42528 50 ds586pp5 in the receiver mode control (address 1eh) register to set the appropriate sample rate. 6.4.5 receiver de-emphas is control (rcvr_dem) default = 0 function: when enabled, de-emphasis will be automatically applied when emphasis is detected based on the channel status bits. the appropriate digital filter will be sele cted to maintain the standard 15 s/50 s digital de-emphasis filter response at the auto-detec ted sample rate of either 32, 44.1, or 48 khz. if the frc_pll_lk bit is set to a ?1?b, then the auto-detect sample rate feature is disabled. to apply the correct de-emphasis filter, use the de-emph bi ts in the receiver mode control (address 1eh) register to set the appropriate sample rate. 6.5 interface formats (address 04h) 6.5.1 digital interface format (difx) default = 01 function: these bits select the digital inte rface format used for the codec serial port and serial audio interface port when not in one_line mode. the required relations hip between the left/right clock, serial clock and serial data is defined by the digital interface fo rmat and the options are detailed in figures 11-12. dac_dem reg03h[1] frc_pll_lk reg06h[0] de-emph[1:0] reg1eh[5:4] de-emphasis mode 0 x xx no de-emphasis 1 0 xx auto-detect fs 11 00 01 10 11 reserved 32 khz 44.1 khz 48 khz table 5. dac de-emphasis rcvr_dem reg03h[0] frc_pll_lk reg06h[0] de-emph[1:0] reg1eh[5:4] de-emphasis mode 0 x xx no de-emphasis 1 0 xx auto-detect fs 11 00 01 10 11 reserved 32 khz 44.1 khz 48 khz table 6. receiver de-emphasis 76543210 dif1 dif0 adc_ol1 adc_ol0 dac_ol1 dac_ol0 sai_rj16 codec_rj16
ds586pp5 51 cs42528 6.5.2 adc one_line mode (adc_olx) default = 00 function: these bits select which mode the adc will use. by de fault one-line mode is disabled but can be se- lected using these bits. please see figures 13 and 14 to see the format of one-line mode 1 and one-line mode 2. 6.5.3 dac one_line mode (dac_olx) default = 00 function: these bits select which mode the dac will use. by default one-lin e mode is disabled but can be se- lected using these bits. please see figures 13 and 14 to see the format of one-line mode 1 and one-line mode 2. 6.5.4 sai right justified bits (sai_rj16) default = 0 function: this bit determines how many bits to use during right-justified mode for the serial audio interface port. by default the receiver will be in rj24 bits but can be set to rj16 bits. 0 - 24 bit mode. 1 - 16 bit mode. dif1 dif0 description format figure 00 left justified, up to 24-bit data 011 01 i 2 s, up to 24-bit data 110 10 right justified, 16-b it or 24-bit data 212 11 reserved -- table 7. digital interface formats adc_ol1 adc_ol0 description format figure 00 dif: take the dif setting from reg04h[7:6] -- 01 one-line #1 313 10 one-line #2 414 11 reserved -- table 8. adc one-line mode dac_ol1 dac_ol0 description format figure 00 dif: take the dif setting from reg04h[7:6] -- 01 one-line #1 313 10 one-line #2 414 11 reserved -- table 9. dac one-line mode
cs42528 52 ds586pp5 6.5.5 codec right justified bits (codec_rj16) default = 0 function: this bit determines how many bits to use during ri ght justified mode for the dac and adc within the codec serial port. by default t he dac and adc will be in rj24 bits but can be set to rj16 bits. 0 - 24 bit mode. 1 - 16 bit mode. 6.6 misc control (address 05h) 6.6.1 external adc sclk select (ext adc sclk) default = 0 function: this bit identifies the sclk source for the external adcs attached to the ad cin1/2 ports when using one line mode of operation. 0 - sai_sclk is used as external adc sclk. 1 - cx_sclk is used as external adc sclk. 6.6.2 rmck high impedance (hiz_rmck) default = 0 function: this bit is used to create a high impedance outp ut on rmck when the clock signal is not required. 6.6.3 freeze controls (freeze) default = 0 function: this function will freeze the prev ious output of, and a llow modifications to be made, to the volume control (address 0fh-16h), channel invert (address 17h) and mixing control pair (address 18h-1bh) registers without the changes taking effect until th e freeze is disabled. to make multiple changes in these control port registers ta ke effect simultaneously, enable th e freeze bit, make all register changes, then disable the freeze bit. 6.6.4 interpolation fi lter select (filt_sel) default = 0 function: this feature allows the user to select whether the dac interpolation filter has a fast or slow roll off. for filter characteristics please see ?d/a dig ital filter characteristics? on page 11. 0 - fast roll off. 1 - slow roll off. 76543210 ext adc sclk hiz_rmck reserved freeze filt_sel hpf_freeze codec_sp m/s sai_sp m/s
ds586pp5 53 cs42528 6.6.5 high pass filter freeze (hpf_freeze) default = 0 function: when this bit is set, the internal high-pass filter for the selected channel will be disabled.the current dc offset value will be frozen and continue to be subt racted from the conversi on result. see ?a/d dig- ital filter characteristics? on page 9. 6.6.6 codec serial port mast er/slave select (codec_sp m/s ) default = 0 function: in master mode, cx_sclk and cx_l rck are outputs. internal dividers will divide the master clock to generate the serial clock and left/right clock. in slave mode, cx_sclk and cx_lrck become in- puts. if the internal mclk is sourced from the output of the pll and the sai serial port is in master mode, then one of these conditions must be met for proper operation: 1). the codec serial port, cx_sp, must also be in master mode, 2). if the cx_sp is in slave mode, then cx_lrck and cx_sclk must be present. 6.6.7 serial audio interface serial po rt master/slave select (sai_sp m/s ) default = 0 function: in master mode, sai_sclk and sai_lrck are output s. internal dividers will di vide the master clock to generate the serial clock and left/right clock. in slave mode, sai_sclk and sai_lrck become inputs. if the internal mclk is sourced from the out put of the pll and the sai serial port is in master mode, then one of these conditions must be met for proper operation: 1). the codec serial port, cx_sp, must also be in master mode, 2). if the cx_sp is in slave mode, then cx_lrck and cx_sclk must be present. 6.7 clock control (address 06h) 6.7.1 rmck divi de (rmck_divx) default = 00 function: divides/multiplies the internal mclk, either fr om the pll or omck, by the selected factor. 76543210 rmck_div1 rmck_div0 omck freq1 omck freq0 pll_lrck sw_ctrl1 sw_ctrl0 frc_pll_lk rmck_div1 rmck_div0 description 00 divide by 1 01 divide by 2 10 divide by 4 11 multiply by 2 table 10. rmck divider settings
cs42528 54 ds586pp5 6.7.2 omck frequency (omck freqx) default = 00 function: sets the appropriate frequency for the supplied omck. 6.7.3 pll lock to lrck (pll_lrck) default = 0 0 - disabled 1 - enabled function: when enabled, the internal pll of the cs42528 will lock to the sai _lrck of the sai serial port. 6.7.4 master clock source select (sw_ctrlx) default = 00 function: these two bits, along with the unlock bit in register ?interrupt status (address 20h) (read only)? on page 64, determine the master clock source for the cs42528. when sw_ctrl1 and sw_ctrl0 are set to '00'b, selecting the output of the pll as the internal clock source, and the pll becomes unlocked, then rmck will equal omck, but all in ternal and serial port timings are not valid. when the frc_pll_lk bit is set to ?1?b, the sw_ctrlx bits must be set to ?00?b. if the pll becomes unlocked when the frc_pll_lk bit is set to ?1?b, then rmck will not equal omck. 6.7.5 force pll lock (frc_pll_lk) default = 0 function: this bit is used to enable the pll to lock to t he s/pdif input stream or the sai_lrck with the ab- sence of a clock signal on omck.when set to a ?1?b, the auto-dete ct sample freq uency feature will be disabled and the sw_ctrlx bits must be set to ?00?b. the omck/pll_clk ratio (address 07h) (read only) register contents are not valid and the pll_clk[2:0] bits will be set to ?111?b. use the de-emph[1:0] bits to properly apply de-emphasis filtering. omck freq1 omck freq0 description 00 11.2896 mhz or 12.2880 mhz 01 16.9344 mhz or 18.4320 mhz 10 22.5792 mhz or 24.5760 mhz 11 reserved table 11. omck frequency settings sw_ctrl1 sw_ctrl0 unlock description 00x manual setting, mclk sourced from pll. 01x manual setting, mclk sourced from omck. 100 1 hold, keep same mclk source. auto switch, mclk sourced from omck. 110 1 auto switch, mclk sourced from pll. auto switch, mclk sourced from omck. table 12. master clock source select
ds586pp5 55 cs42528 6.8 omck/pll_clk ratio (address 07h) (read only) 6.8.1 omck/pll_clk ratio (ratiox) default = xxxxxxxx function: this register allows the user to find the exact abs olute frequency of the recovered mclk coming from the pll. this value is represented as an integer (ratio7:6) and a fractional (ratio5:0) part. for example, an omck/pll_clk ratio of 1.5 would be displayed as 60h. 6.9 rvcr status (address 08h) (read only) 6.9.1 digital silence dete ction (digital silence) default = x 0 - digital silence not detected 1 - digital silence detected function: the cs42528 will auto-detect a digita l silence condition when 1548 consecutive zeros have been de- tected. 6.9.2 aes format detection (aes formatx) default = xxx function: the cs42528 will auto-detect the aes format of the incoming s/ pdif stream and display the infor- mation according to the following table. 76543210 ratio7(2 1 )ratio6(2 0 )ratio5(2 -1 )ratio4(2 -2 )ratio3(2 -3 )ratio2(2 -4 )ratio1(2 -5 )ratio0(2 -6 ) 76543210 digital silence aes format2 aes format1 aes format0 active_clk rvcr_clk2 rvcr_clk1 rvcr_clk0 aes format2 aes format1 aes format0 description 000 linear pcm 001 dts-cd 010 dts-ld 011 hdcd 100 iec 61937 101 reserved 110 reserved 111 reserved table 13. aes format detection
cs42528 56 ds586pp5 6.9.3 system clock sel ection (active_clk) default = x 0 - output of pll 1 - omck function: this bit identifies the source of the internal system clock (mclk). 6.9.4 receiver clock frequency (rcvr_clkx) default = xxx function: the cs42528 will auto-de tect the ratio between th e omck and the recovere d clock from the pll, which is displayed in register 07h. based on this ratio, the absolute frequency of the pll clock can be determined, and this information is displayed ac cording to the following table. if the absolute fre- quency of the pll clock does no t match one of th e given frequencies, this register will display the closest available value. note: these bits are set to ?111?b when the frc_pll_lk bit is ?1?b. 6.10 burst preamble pc and pd bytes (addresses 09h - 0ch)(read only) 6.10.1 burst preamble bits (pcx & pdx) default = xxh function: the pc and pd burst preamble bytes are loaded into these four registers. rcvr_clk2 rcvr_clk1 rcvr_clk0 description 000 8.1920 mhz 001 11.2896 mhz 010 12.288 mhz 011 16.3840 mhz 100 22.5792 mhz 101 24.5760 mhz 110 45.1584 mhz 111 49.1520 mhz table 14. receiver clock frequency detection 76543210 pcx-7 pcx-6 pcx-5 pcx-4 pcx-3 pcx-2 pcx-1 pcx-0 pdx-7 pdx-6 pdx-5 pdx-4 pdx-3 pdx-2 pdx-1 pdx-0
ds586pp5 57 cs42528 6.11 volume transition control (address 0dh) 6.11.1 single volume control (sngvol) default = 0 function: the individual channel volume levels are independent ly controlled by their re spective volume control registers when this function is disabled. when enab led, the volume on all ch annels is determined by the a1 channel volume control register and the other volume control registers are ignored. 6.11.2 soft ramp and ze ro cross control (szcx) default = 00 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audi ble artifacts. the request ed level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero cros sing. the zero cross function is independently mon- itored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to th e new level at a rate of 1 db per 8 left/right clock periods. soft ramp on zero crossing soft ramp and zero cross enable dictates that sign al level changes, either by attenuation changes or muting, will occur in 1/8 db steps and be implement ed on a signal zero cr ossing. the 1/8 db level change will occur after a ti meout period between 512 and 1024 samp le periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not enco unter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 76543210 reserved sngvol szc1 szc0 amute mute sai_sp ramp_up ramp_dn
cs42528 58 ds586pp5 6.11.3 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converters of the cs42528 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. a singl e sample of non-static data will release the mute. detection and muting is done independently for ea ch channel. the quiescent voltage on the output will be retained and the mutec pin will go active duri ng the mute period. the mu ting function is af- fected, similar to volume control changes, by the soft and zero cr oss bits (szc[1:0]). 6.11.4 serial audio interface ser ial port mute (mute sai_sp) default = 0 0 - disabled 1 - enabled function: when enabled, the serial audio inte rface port (sai_sp) will be muted. 6.11.5 soft volume ramp-up after error (rmp_up) default = 0 0 - disabled 1 - enabled function: an un-mute will be perfor med after executing a f ilter mode change, after a mclk/lrck ratio change or error, and after changing the functional mode. when this feature is enabled, this un-mute is affect- ed, similar to attenuation changes, by the soft and zero cross bits (szc[1:0]). when disabled, an im- mediate un-mute is performed in these instances. note: for best results, it is re commended that this bit be used in conjunction with the rmp_dn bit. 6.11.6 soft ramp-down before filter mode change (rmp_dn) default = 0 0 - disabled 1 - enabled function: a mute will be performed prior to ex ecuting a filter mode or de-emp hasis mode change. when this feature is enabled, this mute is af fected, similar to attenuation changes, by the soft and zero cross bits (szc[1:0]). when disabled, an immediate mute is performed prior to executing a filter mode or de-emphasis mode change. note: for best results, it is re commended that this bit be used in conjunction with the rmp_up bit.
ds586pp5 59 cs42528 6.12 channel mute (address 0eh) 6.12.1 independent channel mute (xx_mute) default = 0 0 - disabled 1 - enabled function: the digital-to-analog conv erter outputs of the cs42528 will mute when enabled. the quiescent volt- age on the outputs will be retained. the muting func tion is affected, similar to attenuation changes, by the soft and zero cr oss bits (szc[1:0]). 6.13 volume control (addresses 0fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h) 6.13.1 volume co ntrol (xx_vol) default = 0 function: the digital volume control register s allow independent control of the signal levels in 0.5 db incre- ments from 0 to -127 db. volume settings are decoded as shown in table 15. the volume changes are implemented as dictated by the soft and zero cro ss bits (szc[1:0]). all volume settings less than -127 db are equivalent to enabling the mute bit for the given channel. 6.14 channel invert (address 17h) 6.14.1 invert signal polarity (inv_xx) default = 0 0 - disabled 1 - enabled function: when enabled, these bits will invert the sign al polarity of their respective channels. 76543210 b4_mute a4_mute b3_mute a3_mute b2_mute a2_mute b1_mute a1_mute 76543210 xx_vol7 xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 binary code decimal value volume setting 00000000 0 0 db 00101000 40 -20 db 01010000 80 -40 db 01111000 120 -60 db 10110100 180 -90 db table 15. example digital volume settings 76543210 inv_b4 inv_a4 inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1
cs42528 60 ds586pp5 6.15 mixing control pair 1 (channels a1 & b1)(address 18h) mixing control pair 2 (channels a2 & b2)(address 19h) mixing control pair 3 (channels a3 & b3)(address 1ah) mixing control pair 4 (channels a4 & b4)(address 1bh) 6.15.1 channel a volume = channel b volume (px_a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are independently controlle d by the a and the b channel volume control registers when this function is disabled. the volume on both aoutax and aoutbx are determined by the a channel volume control registers (per a-b pair), and the b channel volume control registers are ignored when this function is enabled. 76543210 px_a=b reserved reserved px_atapi4 px_atapi3 px_atapi2 px_atapi1 px_atapi0
ds586pp5 61 cs42528 6.15.2 atapi channel mixing and muting (px_atapix) default = 01001 function: the cs42528 implements the channel mixing func tions of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 16 and figure 8 for additional information. atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 00000 mute mute 00001 mute br 00010 mute bl 00011 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 01100 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 01111 a[(l+r)/2] b[(l+r)/2] 10000 mute mute 10001 mute br 10010 mute bl 10011 mute [(al+br)/2] 10100 ar mute 10101 ar br 10110 ar bl 10111 ar [(bl+ar)/2] 11000 al mute 11001 al br 11010 al bl 11011 al [(al+br)/2] 11100 [(al+br)/2] mute 11101 [(al+br)/2] br 11110 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] table 16. atapi decode
cs42528 62 ds586pp5 6.16 adc left channel gain (address 1ch) 6.16.1 adc left channel gain (lgainx) default = 00h function: the level of the left analog channel can be adjusted in 1 db increments as dictated by the soft and zero cross bits (szc[1:0]) from +15 to -15 db. levels are decoded in two?s complement, as shown in table 17. 6.17 adc right channel gain (address 1dh) 6.17.1 adc right channel gain (rgainx) default = 00h function: the level of the right analog channel can be adjusted in 1 db increments as dictated by the soft and zero cross bits (szc[1:0]) from +15 to -15 db. levels are decoded in two?s complement, as shown in table 17. 6.18 receiver mode control (address 1eh) 6.18.1 serial port syn chronization (sp_sync) default = 0 0 - cx & sai serial port timings not in phase 1 - cx & sai serial port timings are in phase function: forces the lrck and sclk from the cx & sai serial ports to align and operate in phase. this func- tion will operate when both ports are running at the same sample rate or when operating at different sample rates. 76543210 reserved reserved lgain5 lgain4 lgain3 lgain2 lgain1 lgain0 76543210 reserved reserved rgain5 rgain4 rgain3 rgain2 rgain1 rgain0 binary code decimal value volume setting 001111 +15 +15 db 001010 +10 +10 db 000101 +5 +5 db 000000 0 0 db 111011 -5 -5 db 110110 -10 -10 db 110001 -15 -15 db table 17. example adc input gain settings 76543210 sp_sync reserved de-emph1 de-emph0 int1 int0 hold1 hold0
ds586pp5 63 cs42528 6.18.2 de-emphasis select bits (de-emphx) default = 00 00 - reserved 01 - de-emphasis for 32 khz sample rate. 10 - de-emphasis for 44.1 khz sample rate. 11 - de-emphasis for 48 khz sample rate. function: used to specify which de-emphasi s filter to apply when the ?force pll lock (frc_pll_lk)? on page 54 is enabled. 6.18.3 interrupt pin control (intx) default = 00 00 - active high; high output indicates interrupt condition has occurred 01 - active low, low output indicate s an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved function: determines how the interr upt pin (int) will indicate an interrup t condition. 6.18.4 audio sample hold (holdx) default = 00 00 - hold the last valid audio sample 01 - replace the current audio sample with 00 (mute) 10 - do not change the received audio sample 11 - reserved function: determines how received audio samples are affected when a receiver error occurs. 6.19 receiver mode control 2 (address 1fh) 6.19.1 txp multiplexer (tmuxx) default = 000 function: selects which of the eight receiver inputs will be mapped directly to the txp output pin. 76543210 reserved tmux2 tmux1 tmux0 reserved rmux2 rmux1 rmux0 tmux2 tmux1 tmux0 description 000 output from pin rxp0 001 output from pin rxp1 010 output from pin rxp2 011 output from pin rxp3 100 output from pin rxp4 101 output from pin rxp5 table 18. txp output selection
cs42528 64 ds586pp5 6.19.2 receiver multiplexer (rmuxx) default = 000 function: selects which of the eight receiver inputs will be mapped to th e internal receiver. 6.20 interrupt status (address 20h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has o ccurred at least once since the register was last read. a ?0? means the associated interrupt conditi on has not occurred since the last reading of the register. reading the register resets all bits to 0. status bits that are masked off in the associated mask register will always be ?0? in this register. 6.20.1 pll unlock (unlock) default = 0 function: pll unlock status bit. this bit will go high if the pll becomes unlocked. 6.20.2 new q-subc ode block (qch) default = 0 function: indicates when the q-subcode block has changed. 6.20.3 d to e c-buff er transfer (detc) default = 0 function: indicates when the channel status buffer has changed. 110 output from pin rxp6 111 output from pin rxp7 rmux2 rmux1 rmux0 description 000 input from pin rxp0 001 input from pin rxp1 010 input from pin rxp2 011 input from pin rxp3 100 input from pin rxp4 101 input from pin rxp5 110 input from pin rxp6 111 input from pin rxp7 table 19. receiver input selection 76543210 unlock reserved qch detc detu reserved overflow rerr tmux2 tmux1 tmux0 description table 18. txp output selection
ds586pp5 65 cs42528 6.20.4 d to e u-buff er transfer (detu) default = 0 function: indicates when the user st atus buffer has changed. 6.20.5 adc overflow (overflow) default = 0 function: indicates that there is an over-range condit ion anywhere in the cs42528 adc signal path. 6.20.6 receiver error (rerr) default = 0 function: indicates that a receiver error has occurred. the regi ster ?receiver errors (address 26h) (read only)? on page 68 may be read to determine the nature of the error which caused the interrupt. 6.21 interrupt mask (address 21h) default = 00000000 function: the bits of this register serve as a mask for the inte rrupt sources found in the register ?interrupt status (address 20h) (read only)? on page 64. if a mask bi t is set to 1, the error is unmasked, meaning that its occurrence will affect the int pin and the status register . if a mask bit is set to 0, the error is masked, meaning that its oc currence will not affect the int pin or t he status register. the bit positions align with the corresponding bits in the interrupt status register. 6.22 interrupt mode msb (address 22h) interrupt mode lsb (address 23h) default = 00000000 function: the two interrupt mode registers form a 2-bit code for each interrupt status register function. there are three ways to set the int pin active in accordan ce with the interrupt cond ition. in the rising edge active mode, the int pin becomes ac tive on the arrival of the interr upt condition. in the falling edge active mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level(active high or low) only depends on the int(1: 0) bits located in the register ?receiver mode control (address 1eh)? on page 62. 00 - rising edge active 76543210 unlockm reserved qchm detcm detum reserved overflowm rerrm 76543210 unlock1 reserved qch1 detc1 detu1 reserved of1 rerr1 unlock0 reserved qch0 detc0 detu0 reserved of0 rerr0
cs42528 66 ds586pp5 01 - falling edge active 10 - level active 11 - reserved 6.23 channel status data buffer control (address 24h) 6.23.1 spdif receiver locking mode (lockm) default = 1 0 - revision c compatibility mode. 1 - revision d default mode. provides improved wideband jitter rejection in double and quad speed modes. function: selects the mode used by the spsdif receiver to lo ck to the active rxp[7:0] input. revision c com- patibility mode is included for ba ckward compatibility with revision c. 6.23.2 data buffer select (bsel) default = 0 0 - data buffer address space contains channel status data 1 - data buffer address space contains user data function: selects the data buffer register addresses to contain either user data or channel status data. 6.23.3 c-data buffer control (cam) default = 0 0 - one byte mode 1 - two byte mode function: sets the c-data buffer control port access mode. 6.23.4 channel select (chs) default = 0 function: when set to ?0?, channel a information is displayed in the receiver channel status register. channel a information is output during control port r eads when cam is set to ?0? (one byte mode). when set to ?1?, channel b information is displayed in the receiver channel status register. channel b information is output during control port r eads when cam is set to ?0? (one byte mode). 76543210 reserved lockm reserved reserved reserved bsel cam chs
ds586pp5 67 cs42528 6.24 receiver channel status (address 25h) (read only) the bits in this register can be associated with either channel a or b of the received data. the desired channel is selected with the chs bit of the channe l status data buffer control register. 6.24.1 auxiliary data width (auxx) default = xxxx function: displays the incoming auxiliary data field width, as indicated by t he incoming channel status bits, de- coded according to iec60958. 6.24.2 channel status block format (pro) default = x function: indicates the channel status block format. 6.24.3 audio indicator (audio ) default = x function: a ?0? indicates that the received data is linearly coded pcm audio. a ?1? indicates that the received data is not linearly coded pcm audio. 6.24.4 scms copyright (copy) default = x function: a ?0? indicates that copyright is no t asserted, while a ?1? indicates that copyright is asserted. if the cat- egory code is set to general in the incoming s/pdif digital stream , copyright will always be indicated by copy, even when the stream indicates no copyright. 6.24.5 scms generation (orig) default = x 76543210 aux3 aux2 aux1 aux0 pro audio copy orig aux3 aux2 aux1 aux0 description 0 0 0 0 auxiliary data is not present 0 0 0 1 auxiliary data is 1 bit long 0 0 1 0 auxiliary data is 2 bit long 0 0 1 1 auxiliary data is 3 bit long 0 1 0 0 auxiliary data is 4 bit long 0 1 0 1 auxiliary data is 5 bit long 0 1 1 0 auxiliary data is 6 bit long 0 1 1 1 auxiliary data is 7 bit long 1 0 0 0 auxiliary data is 8 bit long 1 0 0 1 1001 - 1111 is reserved table 20. auxiliary data width selection
cs42528 68 ds586pp5 function: a ?0? indicates that the received data is 1st generation or higher. a ?1? indicates that the received data is original. copy and orig will both be set to ?1? if the incoming data is flagged as professional, or if the receiver is not in use. 6.25 receiver errors (address 26h) (read only) 6.25.1 crc error (qcrc) default = x 0 - no error 1 - error function: indicates a q-subcode data crc error. this bit is updated on q-subcode block boundaries. 6.25.2 redundancy check (ccrc) default = x 0 - no error 1 - error function: indicates a channel status block c yclic redundancy. this bit is upda ted on cs block boundaries, valid in professional mode. 6.25.3 pll lock status (unlock) default = x 0 - pll locked 1 - pll out of lock function: indicates the lock status of the pll. 6.25.4 received validity (v) default = x 0 - data is valid and is no rmally linear coded pcm audio 1 - data is invalid, or ma y be valid compressed audio function: indicates the received validity status. this bit is updated on sub-frame boundaries. 6.25.5 received confidence (conf) default = x 0 - no error 1 - confidence error. the logical or of unlock and bip. the input data stream may be near an error condition due to jitter. function: 76543210 reserved qcrc ccrc unlock v conf bip par
ds586pp5 69 cs42528 indicates the received confidence status. th is bit is updated on sub-frame boundaries. 6.25.6 bi-phase error (bip) default = x 0 - no error 1 - bi-phase error. this indicates an error in the received bi-phase coding. function: indicates a bi-phase coding error. this bit is updated on sub-frame boundaries. 6.25.7 parity status (par) default = x 0 - no error 1 - parity error function: indicates the parity status. this bit is updated on sub-frame boundaries. 6.26 receiver errors mask (address 27h) default = 00000000 function: the bits in this register serve as masks for the corresponding bits of the receiver errors register. if a mask bit is set to 1, the error is unmasked, me aning that its occurrence will appear in the receiver errors register, will affect the re rr interrupt, and will affe ct the current audio sa mple according to the status of the hold bit. if a mask bit is set to 0, the error is masked, meanin g that its occurrence will not appear in the receiver error register, will not affect the re rr interrupt, and will not affect the cur- rent audio sample. the cc rc and qcrc bits behave diffe rently from the other bi ts: they do not affect the current audio sample even when unmasked. 6.27 mutec pin control (address 28h) 6.27.1 mutec polarity select (mcpolarity) default = 0 0 - active low 1 - active high function: determines the polarity of the mutec pin. 6.27.2 channel mutes select (m_aoutxx) default = 11111 76543210 reserved qcrcm ccrcm unlockm vm confm bipm parm 76543210 reserved reserved mcpolarity m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4
cs42528 70 ds586pp5 0 - channel mute is not mapped to the mutec pin 1 - channel mute is mapped to the mutec pin function: determines which channel mutes w ill be mapped to the mutec pin. if no channel mute bits are mapped, then the mutec pin is driven to the "activ e" state as defined by the polarity bit. these channel mute select bits are "anded" together in order for the mutec pin to go active. this means that if multiple channel mutes are selected to be mapped to the mutec pin, then all corresponding channels must be muted before the mutec will go active. 6.28 rxp/general purpose pin control (addresses 29h to 2fh) 6.28.1 mode co ntrol (modex) default = 00 00 - rxp input 01 - mute mode 10 - gpo/overflow mode 11 - gpo, drive high mode function: rxp input - the pin is configured as a receiver input which can then be muxed to either the txp pin or to the internal receiver. mute mode - the pin is configured as a dedicated mute pin. the muting function is controlled by the function bits. gpo, drive low / adc overflow mode - the pin is configured as a general purpose output driven low or as a dedicated adc overflow pin indicating an over-range condition anywhere in the adc signal path for either the left or right channel. the func tionx bits determine the op eration of the pin. when configured as a gpo with the output driven low, the driver is a cmos driver. when configured to iden- tify an adc overflow condition, the driver is an open drain driver requiring a pull-up resistor. gpo, drive high mode - the pin is configured as a general purpose output driven high. 6.28.2 polarity select (polarity) default = 0 function: rxp input - if the pin is configured for an rxp input, the polarity bit is ignored. it is recommended that in this mode this bit be set to 0. mute mode - if the pin is configured as a dedicated mute output pin, then the polarity bit determines the polarity of the mapped pin according to the following 0 - active low 1 - active high gpo, drive low / adc overflow mode - if the pin is configured as a gpo, drive low / adc overflow mode pin, the polarity bit is ignored. it is reco mmended that in this mode this bit be set to 0. gpo, drive high - if the pin is configured as a general pur pose output driven high, the polarity bit is 76543210 mode1 mode0 polarity function4 func tion3 function2 function1 function0
ds586pp5 71 cs42528 ignored. it is recommended that in this mode this bit be set to 0. 6.28.3 functional co ntrol (functionx) default = 00000 function: rxp input - if the pin is configured for an rxp input, the functional bits are ignored. it is recommended that in this mode all the f unctional bits be set to 0. mute mode - if the pin is configured as a dedicated mute pin, then the functional bits determine which channel mutes will be mapped to this pin according to the following table. 0 - channel mute is not mapped to the rxpx/gpox pin 1 - channel mute is mapped to the rxpx/gpox pin: gpo, drive low / adc overflow mode - if the pin is configured as a gpo, drive low / adc overflow mode pin, then the func tion1 and function0 bits determine ho w the output will behave according to the following table. it is recommended that in this mode the remaining functional bits be set to 0. gpo, drive high - if the pin is configured as a general pur pose output, then the functional bits are ignored and the pin is driven high. it is recommended th at in this mode all the functional bits be set to 0. rxpx/gpox reg address function4 function3 function2 function1 function0 rxp7/gpo7 pin 42 29h m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp6/gpo6 pin 43 2ah m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp5/gpo5 pin 44 2bh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp4/gpo4 pin 45 2ch m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp3/gpo3 pin 46 2dh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp2/gpo2 pin 47 2eh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 rxp1/gpo1 pin 48 2fh m_aouta1 m_aoutb1 m_aouta2 m_aoutb2 m_aouta3 m_aoutb3 m_aouta4 m_aoutb4 function1 function0 gpox driver type 00 drive low cmos 11 ovfl r or l open drain
cs42528 72 ds586pp5 6.29 q-channel subcode bytes 0 to 9 (addresses 30h to 39h) (read only) these ten registers contain the decoded q-channel subcode data. 6.30 c-bit or u-bit data buffer (addresses 3ah to 51h) (read only) either channel status data buffer e or user data bu ffer e is accessible through these register addresses. 76543210 address3 address2 address1 address0 control3 control2 control1 control0 track7 track6 track5 track4 track3 track2 track1 track0 index7 index6 index5 index4 index3 index2 index1 index0 minute7 minute6 minute5 minute4 minute3 minute2 minute1 minute0 second7 second6 second5 second4 second3 second2 second1 second0 frame7 frame6 frame5 frame4 frame3 frame2 frame1 frame0 zero7 zero6 zero5 zero4 zero3 zero2 zero1 zero0 a.minute7 a.minute6 a.minute5 a.minute4 a.minute3 a.minute2 a.minute1 a.minute0 a.second7 a.second6 a.second5 a.second4 a.second3 a.second2 a.second1 a.second0 a.frame7 a.frame6 a.frame5 a.frame4 a.frame3 a.frame2 a.frame1 a.frame0 76543210 cu buffer7 cu buffer6 cu buffer5 cu buffer4 cu buffer3 cu buffer2 cu buffer1 cu buffer0
ds586pp5 73 cs42528 7. parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise rati o measurement over the specified band width made with a -60 dbfs signal. 60 db is added to resulting me asurement to refer the measurement to full-scale. this technique ensures that the di stortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 hz to 20 khz), including distortion component s. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with no signal to the input under test and a fu ll-scale signal applied to th e other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
cs42528 74 ds586pp5 8. references 1) cirrus logic, audio quality measurement specification , version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998. 3) cirrus logic, an22: overview of digital audio interface data structures , version 2.0, february 1998.; a useful tutorial on digital audio specifications. 4) cirrus logic, an134: aes and s/ pdif recommended transformers , version 2, april 1999. 5) cirrus logic, an understanding and implementatio n of the scms serial copy management system for digital audi o transmission , by clifton sanchez.; an excellent tu torial on scms. it is available from the aes as preprint 3518. 6) cirrus logic, techniques to measure and maximize the performance of a 120 db, 96 khz a/d con- verter integrated circuit , by steven harris, steven green and ka leung. presented at the 103rd con- vention of the audio engineering society, september 1997. 7) cirrus logic, a stereo 16-bit delta-sigma a/d converter for digital audio , by d.r. welland, b.p. del signore, e.j. swanson, t. tanaka, k. hamashita, s. hara, k. takasuka. paper presented at the 85th convention of the audio engineer ing society, november 1988. 8) cirrus logic, the effects of sampling clock jitter on nyquist sampling analog-to-digital converters, and on oversampling delta sigma adc's , by steven harris. paper presented at the 87th convention of the audio engineering society, october 1989. 9) cirrus logic, an 18-bit dual-channel oversampling de lta-sigma a/d converter, with 19-bit mono ap- plication example , by clif sanchez. paper presented at the 87th convention of the audio engineering society, october 1989. 10) cirrus logic, how to achieve optimum perfor mance from delta-sigma a/d and d/a converters ,by steven harris. presented at the 93rd convention of the audio engineering society, october 1992. 11) cirrus logic, a fifth-order delta-sigma modulator with 110 db audio dynamic range , by i. fujimori, k. hamashita and e.j. swanson. paper presented at the 93rd convention of the audio engineering society, october 1992. 12) international electrotechnical commission, iec60958, http://www.ansi.org 13) philips semiconductor, the i2c- bus specification: version 2.1 , january 2000. http://www.semicon- ductors.philips.com
ds586pp5 75 cs42528 9. package dimensions thermal characteristics inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 d1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e 0.461 0.472 bsc 0.484 11.70 12.0 bsc 12.30 e1 0.390 0.393 bsc 0.398 9.90 10.0 bsc 10.10 e* 0.016 0.020 bsc 0.024 0.40 0.50 bsc 0.60 l 0.018 0.024 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 parameter symbol min typ max units allowable junction temperature - - +135 c junction to ambient thermal impedance ja -48 -c/watt 64l lqfp package drawing e1 e d1 d 1 e l b a1 a
cs42528 76 ds586pp5 10. appendix a: external filters 10.1 adc input filter the analog modulator samples the input at 6.144 mhz (internal mclk=12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are (n 6.144 mhz) the digital passband frequency, where n=0,1,2,... refer to figure 24 for a recommended analog input buffer that will attenuate any noise energy at 6.144 mhz, in addition to providing the optimum source impedance for the modulators. the use of capac itors which have a large voltage coefficient (such as general purpose ceramics) must be avoi ded since these can degrade signal linearity. 10.2 dac output filter the cs42528 is a linear phase design and does not in clude phase or amplitude compensation for an ex- ternal filter. therefore, the dac system phase and amplitude response will be dependent on the external analog circuitry. va + + - - 100 f 100 k ? 10 k ? 3.32 k ? 2.8 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g ainl1+ ainl1- ainr1+ ainr1- va + + - - 100 f 100 k ? 10 k ? 3.32 k ? 2.8 k ? 0.1 f 100 f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g 332 ? 332 ? figure 24. recommended analog input buffer ainl ainr aout + aout - - + 390 pf c0g 1 k ? 22 f 6.19 k ? 1800 pf c0g 887 ? 2.94 k ? 5.49 k ? 1.65 k ? 1.87 k ? 22 f 1200 pf c0g 5800 pf c0g 47.5 k ? analog out figure 25. recommended analog output buffer
ds586pp5 77 cs42528 11. appendix b: s/pdif receiver 11.1 error reporting a nd hold function the unlock bit indicates whether the pll is locked to the incoming s/pdif data. the v bit reflects the current validity bit status. the conf (confidence) bi t indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. the bip (bi-phase) error bit indicates an error in incom- ing bi-phase coding. the par (parity) bi t indicates a received parity error. the error bits are "sticky": they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. this enables the register to log all unmasked errors that occurred since the last time the register was read. the receiver errors mask register (see ?receiver e rrors mask (address 27h)? on page 69) allows mask- ing of individual errors. the bits in this register serve as masks for the corre sponding bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error register, invoke the occurrence of a rerr interrupt, and affect the current audio sample according to the status of the hold bits. the hold bits allow a choice of holding the previous sample, replacing the current sample wi th zero (mute), or not changing the current audio sample. if a mask bit is set to 0, the error is masked, which implies the following: its occurrence will not be reported in the receiver error register, the rerr interrupt will not be generated, and the current audio sample will not be affected. the qcrc and ccrc erro rs do not affect the current audio sample, even if unmasked. 11.2 channel status data handling the setting of the chs bit in the register ?channel status data buffer control (address 24h)? on page 66 determines whether the channel status decodes are from the a channel (chs = 0) or b channel (chs = 1). the pro (professional) bit is extrac ted directly. for consumer data, th e copy (copyright) bit is extracted, and the category code and l bits are decoded to determine scms status, indicated by the orig (original) bit. if the category code is set to general on the incoming s/pdif stream, copyright will always be indi- cated even when the stream indicate s no copyright. finally, the audio bit is extracted and used to set an audio indicator, as described in section 4.4.5, non-audio auto-detection. if 50/15 s pre-emphasis is detected, and the receiv er auto de-emphasis control is enabled, then de- emphasis will automatically be appli ed to the incoming digital pcm data. see ?functional mode (address 03h)? on page 49 for more details. the encoded channel status bits which indicate sample word length are decoded according to iec 60958. audio data routed to the serial audio interface port is unaffected by the word length settings; all 24 bits are passed on as received. the cs42528 also contains sufficient ram to store a full block of c data for both a and b channels (192 x 2 = 384 bits), and also 384 bits of user (u data) information. the user may read from these buffer rams through the control port. the buffering scheme involves 2 block-sized buffers , named d and e, as shown in figure 26. the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 4ah) is the consumer/p rofessional bit for channel status block a. the first buffer (d) accepts incoming c data from the s/pdif receiver. the 2nd buffer (e) accepts entire blocks of data from the d buffer. the e buffer is also accessible from the control port, allowing reading of the c data.
cs42528 78 ds586pp5 11.2.1 channel status data e buffer access the user can monitor the incoming channel status data by reading the e buffer, which is mapped into the register space of the cs42528, through the control port data buffer. the data buffer must first be config- ured to point to the address space of the c data. this is accomplished by setting the bsel bit to ?0? in the register ?channel status data buffer control (address 24h)? on page 66. the user can configure the interrupt mask register to cause an interrupt whenever any data bit changes are detected when d to e channel status buffer transfers occur. if no data bits have changed within the current transfer of data from d to e, then no interr upt will be generated. this allows determination of the acceptable time periods to interact with the e buffer. see ?interrupt mask (address 21h)? on page 65 for more details. the e buffer is organized as 24 x 16-bit words. for each word the ms byte is the a channel data, and the ls byte is the b channel data (see figure 26). ther e are two methods of accessing this memory, known as one byte mode and two byte mode. the desired mode is selected by setting the cam bit in the channel status data buffer control register. 11.2.1a one byte mode in many applications, the channel stat us blocks for the a and b channels w ill be identical. in this situation, the user may read a byte from one of the channel's blocks since the corresponding byte for the other chan- nel will likely be the same. one byte mode takes advantage of the often identical nature of a and b chan- nel status data. when reading data in one byte mode, a single byte is returned, which can be from channel a or b data, depending on a register control bit. one byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access ti me. if the control port's autoincrement addressing is used in combination with this mode, multi-byte accesses such as full-block reads can be done especially effi- ciently. 11.2.1b two byte mode there are those applications in which the a and b channel status blocks will not be the same, and the user is interested in accessing both blocks. in thes e situations, two byte mode should be used to access the e buffer. in this mode, a read will cause the cs42528 to output two bytes from its control port. the first byte out will represent the a channel status data, and the sec ond byte will represent the b channel status data. control port from s/pdif receiver e 24 words 8-bits 8-bits ab d received data buffer figure 26. channel status data buffer structure
ds586pp5 79 cs42528 11.2.2 serial copy management system (scms) the cs42528 allows read access to all the channel status bits. for consum er mode scms compliance, the host microcontroller needs to read and interpret the category code, copy bit and l bit appropriately. 11.3 user (u) data e buffer access entire blocks of u data are buffered using a cascade of 2 block-sized rams to perform the buffering as described in the channel status section. the user has access to the e buffer through the control port data buffer which is mapped into the register space of th e cs42528. the data buffer must first be configured to point to the address space of the u data. this is ac complished by setting the bsel bit to ?1? in the reg- ister ?channel status data buffer control (address 24h)? on page 66. the user can configure the interrupt mask register to cause an interrupt whenever any data bit changes are detected when d to e channel status buffer transfers occur. if no data bits have changed within the current transfer of data from d to e, then no interr upt will be generated. this allows determination of the acceptable time periods to interact with the e buffer. see ?interrupt mask (address 21h)? on page 65 for more details. the u buffer access only operates in two byte mode, si nce there is no concept of a and b blocks for user data. the arrangement of the data is as follows: bit15[a7]bit14[b7]bit13[a6]bit12[b6]...bit1[a0]bit0[b0]. the arrangement of the data in each byte is as follows: msb is the first received bit and is the first trans- mitted bit. the first byte read is the first byte received, and the first byte sent is the first byte transmitted. when two bytes are read from the e buffer, the bi ts are presented in the following arrangement: a[7]b[7]a[6]b[6]....a[0]b[0]. 11.3.1 non-audio auto-detection the cs42528 s/pdif receiver can detect non-audio data originating from ac-3 ? or mpeg encoders. this is accomplished by looking for a 96-bit sy nc code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872, and 0x4e1f. when the sync code is detected, an internal autodetect signal will be asserted. if no additional sync codes are detected within the next 4096 frames, autodetect will be de-asserted until another sync code is detected. the audio bit in the receiver channel status register is the logical or of autodetect and the received channel status bit 1. if non-audio data is detected, the data will be processed exactly as if it were normal audio. it is up to the user to mute the outputs as required. 11.3.1a format detection the cs42528 can automatically detect various serial audio input formats. the receiver status register (08h) is used to indicate a detected format. the register will indicate if uncompressed pcm data, iec61937 data, dts-ld data, dts-cd data, or digi tal silence was detected . additionally, the iec61937 pc/pd burst preambles are available in registers 09h-0c h. see the register descriptions for more informa- tion.
cs42528 80 ds586pp5 12. appendix c: pll filter the pll has been designed to only use the preambles of the s/pdif stream to provide lock update infor- mation to the pll. this results in the pll being immune to data dependent jitter effects because the s/pdif preambles do not vary with the data. the pll has the ability to lock onto a wide range of input sample rates with no external component chang- es. the nominal center sample rate is the sample ra te that the pll first locks onto upon application of an s/pdif data stream. phase comparator and charge pump n vco rmck input crip cfilt rfilt figure 27. pll block diagram
ds586pp5 81 cs42528 12.1 external fi lter components 12.1.1 general the pll behavior is affected by the external filter component values in the typical connection diagrams. figure 5 show the recommended configuration of the two capacitors and one resistor that comprise the pll filter. the external pll component values listed in table 21 have a high corner frequency jitter atten- uation curve, take a short time to lock, and offer good output jitter performance. lock times are worst case for an fsi transition of 192 khz. it is important to treat the lpfilt pin as a low level analog input. it is suggested that the ground end of the pll filter be returned directly to the agnd pin independently of the digital ground plane. it should be noted that, for backward compatibility with revision c, these components may be used with revision d silicon with the lockm (register 24h, bit 6) set to ?0?. 12.1.2 jitter attenuation shown in figure 28 is the jitter attenuation plot when used with the external pll component values listed in table 21 for the 32-192 khz fs range. the aes3 and iec60958-4 specifications do not have allow- ances for locking to sample rates less than 32 khz or for locking to the sai_lrck input. these specifica- tions state a maximum of 2 db jitter gain or peaking. rfilt (k ? )cfilt ( f) crip (pf) 2.55 0.047 2200 table 21. pll external component values figure 28. jitter attenuation characteristics of pll
cs42528 82 ds586pp5 12.1.3 capacitor selection the type of capacitors used for the pll filter can hav e a significant effect on receiver performance. large or exotic film capacitors are not necessary as t heir leads and the required longer circuit board traces add undesirable inductance to the circui t. surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted clos e to the lpflt pin to minimize trace inductance. for crip, a c0g or npo dielectric is recommended; and for cfilt, an x7r dielectric is preferred. avoid capacitors with large temperature co-coefficient, or c apacitors with high dielectric constants, that are sensitive to shock and vibration. the se include the z5u and y5v dielectrics. 12.1.4 circuit board layout board layout and capacitor choice affect each other and determine the performance of the pll. figure 29 illustrates a suggested layout for the pll f ilter components and for bypassing the analog supply voltage. the 10 f bypass capacitor is an electrolytic in a surface mount case a or thru-hole package. rfilt, cfilt, crip, and the 0.1 f decoupling capacitor are in an 0805 form factor. the 0.01 f decoupling capacitor is in the 0603 form factor. the traces are on the top surface of the board with the ic so that there is no via inductance. the traces themse lves are short to minimize the inductance in the filter path. the varx and agnd traces extend back to their origin and are shown only in truncated form in the drawing. varx agnd lpflt cfilt rfilt crip 0.1 f 0.01 f 10 f = via to ground plane figure 29. recommended layout example
ds586pp5 83 cs42528 13. appendix d: external aes3/spd if/iec60958 receiver components 13.1 aes3 receiver ex ternal components the cs42528 aes3 receiver is de signed to accept only consumer-s tandard interfaces. the standards call for an unbalanced circuit hav ing a receiver impedance of 75 ? 5%. the connector is an rca phono socket. the receiver circuit is shown in figure 30. figure 31 shows an implementat ion of the input s/pdif multiplexer using the consumer interface. in the configuration of systems, it is important to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes wi th different ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advantageous to have the ground of two boxes held at the same potential, and make the electrical connection through the cable shield. generally, it may be a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. when more than one rxp pin is driven simultaneously, as shown in figure 31, there is a potential for crosstalk between inputs. to minimize this crosstalk, provide as much trace separation as is reasonable and choose non-adjacent inputs when possible. the circuit shown in figure 32 may be used when external rs422 receivers, optical receivers or other ttl/cmos logic outputs drive the cs425 28 receiver input. rxp7 rxp0 rxp6 75 ? .01 f .01 f .01 f . . . 75 ? coax 75 ? 75 ? 75 ? coax 75 ? coax figure 30. consumer input circuit figure 31. s/pdif mux input circuit rca phono rxp0 coax 75 ? 75 ? 0.01 f rxp0 0.01 f ttl/cmos gate figure 32. ttl/cmos input circuit
cs42528 84 ds586pp5 14. appendix e: adc filter plots -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 33. single speed mode stopband rejection figure 34. single speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 35. single speed mode transition band (detail) figure 36. single speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 37. double speed mode stopband rejection figure 38. double speed mode transition band
ds586pp5 85 cs42528 ? -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 39. double speed mode transition band (d etail) figure 40. double speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 41. quad speed mode stopband rejectio n figure 42. quad speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 43. quad speed mode transition band (det ail) figure 44. quad speed mode passband ripple
cs42528 86 ds586pp5 15. appendix f: dac filter plots 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 45. single speed (fast) stopband rejection figure 46. single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 47. single speed (fast) tran sition band (detail) figure 48. single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 49. single speed (slow) stopband reject ion figure 50. single speed (slow) transition band
ds586pp5 87 cs42528 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 51. single speed (slow) transition band (d etail) figure 52. single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 53. double speed (fast) stopband rejection figure 54. double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 55. double speed (fast) transition band (detail) figure 56. double speed (fast) passband ripple
cs42528 88 ds586pp5 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 57. double speed (slow) stopband rejectio n figure 58. double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 59. double speed (slow) transition band (d etail) figure 60. double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 61. quad speed (fast) stopband rejection figure 62. quad speed (fast) transition band
ds586pp5 89 cs42528 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 63. quad speed (fast) transition band (d etail) figure 64. quad speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 65. quad speed (slow) stopband rejectio n figure 66. quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 67. quad speed (slow) transition band (detail) figure 68. quad speed (slow) passband ripple
cs42528 90 ds586pp5 table 22. revision history release date changes a1 december 2002 advance release pp1 august 2003 preliminary release pp2 august 2003 ? added revision history table. ? updated registers 6.7.4 and 6.7.5 on page 54. pp3 march 2004 corrected error in document title. pp4 july 2004 add lead free part numbers pp5 january 2005 ? updated pll components in table 21 on page 81. ? added pdn_rcvr1 bit and description on page 48. ? added lockm bit and description on page 66. ? added omck frequency specification in the switching characteristics table on page 12. ? updated adc input impedance and offset error specifications in the analog input characteristics table on page 8. ? updated the dac full scale voltage, output impedance, and gain drift specifications in the analog output characteristics table on page 10. ? updated specification conditions for the analog input characteristics on page 8. ? updated specification conditions for th e analog output characteristics on page 10. ? updated specification of t ds and t dh in the switching characteristics table on page 12. ? corrected reference to the sw_ctrl[1:0] bits in section 4.5.3 on page 26. ? moved the vq and filt+ specifications from the analog input characteristics table on page 8 to the dc electrical characteristics table on page 15. ? updated the power supply current and power consumption specifications in the dc electrical characte ristics table on page 15. ? updated the description of the conf bit on page page 68. ? updated table 13 on page 55 to include hdcd format detection. ? corrected default value of the chip_id[3:0] bits in register 01h on pages 42 and 47. ? updated default value of the rev_id[3:0] bits in register 01h on pages 42 and 47.
ds586pp5 91 cs42528 important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the infor- mation is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and co mplete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to wa rranty, indemnification, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this info rmation as the basis for man- ufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property o f cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, tra de secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. t his consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for re sale. certain applications using semiconductor products may in volve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, autho- rized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security devices, life supp ort products or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, incl uding the implied warranties of merchantability and fit- ness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, dire ctors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. ac-3 is a registered trademark of dolby laboratories, inc. dts is a registered trademark of the digital theater systems, inc. spi is a trademark of motorola, inc. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com/

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